WiFi MAC Design Verification Engineer

As a Wireless MAC Design Verification Engineer, you’ll be instrumental in our WCS group’s verification initiatives, ensuring that our products incorporate cutting-edge Wi-Fi technology while maintaining high quality and reliability. We’re looking for candidates with hands-on experience in the entire ASIC design verification cycle, preferably with expertise in reusable verification methodologies like UVM or similar. This position offers excellent opportunities to deepen your knowledge of Wi-Fi protocols, complex IP and subsystems, and fabric protocols. You’ll also be collaborating closely with system architects, design, software, and firmware teams. The ideal candidate will excel in detailed test planning, adapt to evolving requirements, build test bench infrastructure, perform regressions, close coverage, and leverage various AI tools to streamline DV processes and expedite debugging. Prior knowledge of wireless domain or MAC verification is a plus. If you’re passionate about contributing to products that have a global impact and want to advance your technical expertise, we’d love to hear from you.

Responsibilities:

Own critical block and sub-system verification of WIFI MAC.

Architect and develop test-benches, environments and define new verification methodologies in most innovative environment.

Leverage AI-based tools (such as Claude Code) to accelerate verification workflows, automate testbench development, and enhance productivity.

Learn new most advanced protocols related to IEEE 802.11 Wireless LAN specification.

Create, simulate and debug test scenarios.

Lead regressions and issue tracking.

Collaborate with Design, Systems, SW engineering teams to review specifications and architecture, extract features, and define verification plans.

Knowledge of Wireless Connectivity or MAC verification.

Experience using AI-based tools for verification (e.g., Claude Code or similar) to improve efficiency and automation.

Highly motivated, ambitious, and eager to collaborate effectively in a dynamic and fast-paced work environment.

Minimum Qualifications

Bachelors degree +10 years of relevant experience.

Advanced Knowledge of standard ASIC design and verification flows.

Proven track record in leading the verification methodology for clusters, subsystems, or full-chip level designs.

Deep proficiency in OOP, SystemVerilog, UVM.

Strong analytical and problem-solving skills, with the ability to debug complex design issues effectively.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.