DDR Design Engineer

In this role, you will be responsible for performing concept studies and providing direction in terms of performance, gate count and power for various digital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.

At Apple, we work to craft products that enrich people’s lives. If you’re passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated DDR Design Engineer., RTL design using Verilog or SystemVerilog, including assertion writing.

Experience with design of state machines, data paths, arbitration and clock domain crossing logic.

Experience with logic synthesis, timing constraints.

Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL.

Experience with Unified Power Format for simulation, synthesis and electrical rule checking, and equivalence checking.

Prior experience in DDR PHY design and mixed-signal environment is a plus., Bachelors of Science in Electrical Engineering.