ASIC Architect in Oxfordshire

Own the end-to-end ASIC architecture of a probabilistic computing processor, from algorithm understanding through to tape-out. Define system architecture, instruction set architecture (ISA) and dataflow models based on workload requirements. Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements. Build functional simulations and performance models to guide architectural decisions. Conduct timing, power and area trade-off analysis with strong physical design awareness. Define detailed microarchitecture specifications, including memory hierarchy, connectivity and interface requirements. Lead internal IP development and evaluate third-party IP solutions. Guide designs through verification, sign-off, tape-out and silicon bring-up.

Proven architectural ownership of at least one ASIC taken successfully to tape-out, ideally within compute accelerators, inference engines or DSP applications. Strong hands-on experience with performance modelling, simulation and architectural trade-off analysis using Python, C++ or similar . Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools. Solid understanding of timing, power and area optimisation at the architectural level. Experience defining hardware/software interfaces and collaborating with firmware and compiler teams. Strong RTL design knowledge and experience defining verification strategies from an architectural perspective.

This is a fantastic opportunity to play a pivotal role in developing revolutionary computing technology, influencing product direction and driving innovation from concept through to silicon deployment.