Senior RTL Design Engineer

• Write test plans, define test methodologies, develop C-based software tests, SystemVerilog/Verilog testbenches, and debug test failures and issues.
• Work with project management and leads on planning tasks, schedules, and reporting progress.
• Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development., Join a team of dedicated engineers and be part of our ambitious mission to develop flawless IPs that compete globally! We strictly adhere to the highest standards and provide opportunities to determine and successfully implement innovative solutions. Enjoy a collaborative work environment where your growth is our priority.

• Proven understanding of digital hardware verification languages Verilog/SystemVerilog HDL.
• Skilled in one or more verification approaches - UVM, formal, power aware verification.
• Experience in SoC verification using embedded low-level programming including C/C++ tests and assembly language (preferably ARM).
• Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support.
• Good problem-solving and debugging skills.
• Knowledge of IP/SoC verification flow and strategy.
• Experience with ARM-based builds and/or ARM system architectures.
• Clock domain crossing verification.
• Experience in GLS, DFT/DFD.
• Skilled in UPF power-aware verification.
• Automation experience with shell programming/scripting (e.g., Tcl, Perl, Python).
• Willingness to explore and apply AI based methods to digital verification.

Preferred Skills and Experience

• Exposure to formal verification using JasperGold/VC formal.
• Prior experience in hardware security and cryptographic algorithms.
• Understanding of machine learning algorithms and their applications in verification.
• Knowledge of ARM proprietary tools and environments.