Design for Test Engineer IV

Arrow Electronics is seeking a Design for Test Engineer IV to drive advanced DFT strategy across complex electronic designs in our Engineering & Design organization. You will architect and implement scan, BIST, and boundary scan solutions, optimize test coverage and pattern quality, and collaborate closely with design, verification, and product engineering teams. In this performance-driven, innovative, and collaborative environment, you’ll mentor junior engineers, influence DFT flows and standards, and help ensure high-quality, high-yield products for global industrial and commercial customers., * Architect and implement DFT strategies (scan, BIST, boundary scan) for complex So

• Cs/ASICs and electronic systems.
• Develop and integrate ATPG patterns, analyze coverage, and drive improvements in test quality and manufacturability.
• Collaborate with design, verification, and product engineering teams to ensure DFT requirements are integrated from early design stages.
• Own DFT insertion, verification, and sign-off flows using industry-standard EDA tools.
• Debug silicon and test issues, perform root-cause analysis, and drive corrective actions to improve yield and reliability.
• Define and maintain DFT methodologies, standards, and best practices across the Engineering & Design organization.
• Mentor and technically guide junior engineers on DFT concepts, tools, and flows.
• Support test engineering and manufacturing teams in ramping new products to volume production.
• Document DFT architectures, test plans, and results for internal and external stakeholders.
• Contribute to continuous improvement initiatives, tool evaluations, and automation to enhance DFT efficiency and coverage.

• Design for Testability (DFT) architecture
• Scan insertion and compression
• Built-In Self-Test (BIST) for logic and memory
• Boundary scan / JTAG (IEEE 1149.1/1500/1687)
• ATPG and fault simulation
• Digital IC/So
• C/ASIC design fundamentals
• Scripting (Tcl, Python, or Perl) for EDA automation
• Static timing and constraints awareness for DFTSilicon bring-up and production test debug
• DFT tool expertise (Synopsys, Siemens Tessent, Cadence, etc.)