Hardware Developer - Z, EDA

• Customize Cadence graphical user interfaces (GUIs) based on user requirements using the Cadence SKILL programming language.
• Apply VLSI verification methodologies (e.g. SystemVerilog and UVM) to validate chip functionality, debugging, Tcl scripting, LEX & YACC programming, and carrying out functional coverage analysis.
• Conduct thorough EDA analysis for large scale SoC designs, including noise evaluation, timing analysis, power integrity assessments, and electromigration analysis, ensuring that designs operate reliably under a variety of voltage, temperature, and process conditions.
• Manage timing constraints, identify potential reliability issues at worst case corners, and define mitigation strategies through design optimization and Tcl-based tool enhancements.
• Develop VLSI design tools that support hierarchical integration, floor planning, and timing and power optimization.
• Work across a wide range of Electronic Design Automation (EDA) functions, including power analysis, power grid analysis, chip power rule parsing, and ongoing maintenance and enhancement of complex EDA codebases.
• Lead a team to analyze, maintain, and enhance EDA software toolkits.
• Apply AI, machine learning, and large language model techniques to EDA specific workflows.
• Utilize: EDA methodologies (Tcl, LEX and YACC), Cadence SKILL language development, VLSI verification methodologies using SystemVerilog and Universal Verification Methodology (UVM), hardware description languages (such as Verilog and VHDL), EDA software tool development, EDA-focused AI development.

Required: Master’s degree or equivalent in Computer Science, Computer Engineering or related (employer will accept a Bachelor’s degree plus five (5) years of progressive experience in lieu of a Master’s degree) and one (1) year of experience as an Engineer or related. One (1) year of experience must include utilizing EDA methodologies (Tcl, LEX and YACC), Cadence SKILL language development, VLSI verification methodologies using SystemVerilog and Universal Verification Methodology (UVM), hardware description languages (such as Verilog and VHDL), EDA software tool development, EDA-focused AI development. $167,160 to $217,000 per year. Full time. H601

Required technical and professional expertise

• Master’s degree or equivalent in Computer Science,
• Computer Engineering or related (employer will accept a Bachelor’s degree plus five (5) years of progressive experience in lieu of a Master’s degree) and one (1) year of experience as an Engineer or related.
• One (1) year of experience must include utilizing EDA methodologies (Tcl, LEX and YACC), Cadence SKILL language development, VLSI verification methodologies using SystemVerilog and Universal Verification Methodology (UVM), hardware description languages (such as Verilog and VHDL), EDA software tool development, EDA-focused AI development.