Digital Design Engineer

We are seeking an experienced Senior Digital Design Engineer to join an advanced wireless connectivity development team.

In this role, you will take ownership of digital architecture, RTL design, verification, and FPGA prototyping for next-generation wireless communication solutions. You will work across MAC, PHY, and platform-level subsystems, contributing throughout the full design lifecycle from architecture definition through implementation, verification, validation, and product support.

The position requires strong technical depth, a high degree of autonomy, and the ability to collaborate effectively across system architecture, algorithms, hardware, software, validation, and application engineering teams.

Key Responsibilities

• Take ownership of macro-level and subsystem architecture, design, implementation, and verification for advanced wireless MAC, PHY, and platform solutions.
• Define microarchitecture and hardware interfaces based on system-level requirements.
• Develop high-quality RTL using Verilog and SystemVerilog.
• Implement and prototype digital designs on FPGA platforms integrated with existing firmware and RF environments.
• Develop and maintain verification environments, testbenches, coverage strategies, and co-simulation flows.
• Support synthesis, integration, debugging, and performance optimisation throughout the development lifecycle.
• Work closely with validation teams during product qualification and certification activities.
• Support application and customer-facing engineering teams with technical analysis and issue resolution where required.
• Plan, track, and communicate technical progress, risks, and dependencies.
• Produce clear technical documentation covering subsystem architecture, interfaces, implementation details, and hardware-level testing.
• Mentor engineers and provide technical guidance on architecture, RTL development, verification, and design methodology.
• Drive continuous improvements in design processes, methodologies, development tools, and engineering workflows.
• Collaborate across multidisciplinary teams to ensure performance, reliability, and product requirements are achieved.

• Bachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Embedded Systems, Computer Science, or a related technical discipline.
• Twelve or more years of relevant experience in digital hardware design.
• At least five years of experience in digital or subsystem architecture.
• Deep understanding of SoC architecture and complex digital hardware subsystems.
• Strong hands-on expertise in Verilog and SystemVerilog.
• Experience across the complete digital design lifecycle, including:
• Microarchitecture definition
• RTL implementation
• Testbench development
• Functional and code coverage
• Logic synthesis
• Verification and debugging
• Hardware/software co-simulation
• Strong experience with FPGA implementation and prototyping.
• Excellent analytical and problem-solving skills.
• Ability to work independently and take ownership of complex technical areas.
• Strong planning, organisation, and progress-tracking capability.
• Effective written and verbal communication skills.
• Fluent English.

Preferred Qualifications

• Experience designing digital IP for wireless communication systems.
• Strong understanding of MAC, PHY, or baseband architectures.
• Knowledge of one or more wireless standards, including:
• Bluetooth
• IEEE 802.15.4
• Wi-Fi / IEEE 802.11
• UWB
• Cellular / 3GPP
• Experience integrating digital IP with firmware, RF, or mixed hardware/software platforms.
• Familiarity with low-power SoC design techniques and power-aware implementation.
• Experience with timing closure, CDC analysis, reset-domain analysis, and synthesis constraints.
• Knowledge of ASIC design and verification methodologies.
• Experience supporting silicon bring-up, validation, qualification, or product certification.
• Previous experience mentoring engineers or providing technical leadership within a design team.

Candidate Profile

The successful candidate will combine strong hands-on RTL expertise with system-level architectural understanding.

You should be comfortable owning complex digital subsystems from initial architecture through implementation and verification, while working closely with teams across hardware, software, algorithms, validation, and system engineering., The role is particularly suited to an engineer who can operate independently, provide technical leadership, and contribute directly to the development of high-performance wireless connectivity technologies.