Sr. RTL Design Engineer

You will work from architectural and microarchitectural requirements, turn them into clean and synthesizable SystemVerilog, and partner closely with design verification, physical design, firmware, compiler, and silicon-validation engineers. The ideal candidate is comfortable owning a block from definition through implementation, debug, quality checks, and integration.

• Design, implement, integrate, and debug synthesizable RTL for NNE blocks and interfaces.
• Translate architectural and microarchitectural specifications into clear, maintainable RTL and supporting design documentation.
• Develop pipelined datapaths, control logic, finite-state machines, queues, counters, memory interfaces, and configuration/status logic.
• Define and review block-level interfaces, including data movement, handshakes, clocking, reset behavior, and error handling.
• Develop and utilize AI agents to streamline RTL development tasks
• Design with performance, power, area, functional safety, and physical implementation constraints in mind.
• Collaborate with design verification engineers to create test plans, assertions, coverage goals, and debug strategies.
• Use simulation, lint, CDC/RDC, formal or equivalence checking, synthesis, and timing analysis to evaluate and improve RTL quality.
• Investigate functional, performance, timing, and power issues across RTL, verification, and implementation flows.
• Participate in design reviews and contribute to coding standards, reusable RTL patterns, and development methodology improvements.
• Support block integration, regression closure, RTL handoff, and pre-silicon validation.
• Communicate design decisions, assumptions, risks, and trade-offs clearly across partner teams.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.
• Professional experience designing and delivering synthesizable RTL for ASIC, SoC, or other complex digital hardware.
• Strong proficiency in Verilog and SystemVerilog.
• Understanding of synchronous digital design, pipelining, finite-state machines, interfaces, memories, and reset/clock behavior.
• Experience debugging RTL through simulation and waveform analysis.
• Ability to read and contribute to architectural, microarchitectural, interface, and verification specifications.
• Strong written and verbal communication skills, especially to write clear design documentation, with a collaborative and ownership-oriented approach.
• A disciplined approach to writing simple, readable, reusable, and verifiable RTL.
• Curiosity about how architecture, implementation, verification, and physical design interact.
• Comfort working through ambiguous problems, making explicit assumptions, and iterating with partner teams.
• A bias toward early validation, clear documentation, and high-quality handoffs.
• The ability to balance block-level ownership with system-level thinking., * Experience with compute engines, neural-network accelerators, floating point computation, memory subsystems, high-throughput datapaths, or SoC control logic.
• Experience with clock-domain crossings, reset-domain crossings, clock gating, power-aware design, or functional-safety concepts.
• Familiarity with RTL quality and implementation flows such as lint, CDC/RDC, formal/equivalence checking, synthesis, static timing analysis, and power analysis.
• Experience with Synopsys VCS, Verdi, or comparable simulation and debug tools.
• Experience building Python or other software models to explore architecture, validate behavior, or accelerate RTL development.
• Experience with Git-based development, code review, continuous integration, and automated regressions.
• Familiarity with physical-design constraints and PPA trade-offs.
• Experience working across hardware, firmware, compiler, verification, physical design, and silicon-validation teams.
• Experience developing hardware for automotive, safety-critical, or other reliability-sensitive applications.