Lead Digital Design Verification Engineer

You will be responsible for defining and supporting the adoption of cutting-edge verification tools and methodologies with a focus on AI and Machine Learning. You will have a horizontal role working with multiple projects and teams to accelerate adoption of latest verification best practices. Responsibilities: Develop and support adoption of generative AI tools to create and update, UVM and Formal verification environmentsDevelop methodology guidance and end to end flows to ensure AI tools used in a consistent, efficient and predictable wayDevelop and roll out solutions that reduce verification debug timeAutomate documentation checking to improve quality and consistencyBuild tools and processes to support verification planningOptimise UVM regressions through improved automation and machine learningMaintain and develop best practices for Functional Safety Verification, Gate Level Simulation and Low Power VerificationMaintain and improve design review checklists and quality documentation

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline Experience:4+ years experience in the microelectronics/EDA industryProficiency in System Verilog and assertionsHands-on experience with Metric Driven Verification (MDV)Strong knowledge of constrained-random verification techniques (e.g. UVM)Excellent spoken and written EnglishSelf-motivated, with strong planning, interpersonal, and communication skills Additional Skills/Preferences: Formal verification experience and related applicationsProficiency with scripting languages (e.g. Python)Knowledge of AI agent development (tools, concepts, and infrastructure)Methodology development and change management experienceFamiliarity with front-end design tools (e.g. LINT, CDC analysis)Exposure to quality processes and standards (e.g. ISO 9001, ISO 26262)