Performance Modeling Software Engineer, Platform Architecture

You will be tasked with ensuring Apple’s ability to produce high quality, timely data to drive world class hardware designs. You will collaborate with engineers across the organization to translate design space studies into well written software models. You will develop your ability to transform the hardware execution model into high-performance C++. You will be involved with the full life-cycle of performance modeling, from early architectural exploration to post-silicon correlation. Last, but not least, you’ll be expected to pay close attention to the performance, maintainability, and flexibility of the simulator, making sure hardware architects can quickly iterate on experiments., Appreciate the good parts of C++, and leveraging the language to maximize the utility of our software models

Develop APIs that can be used by non-expert C++ developers

Train AI agents and non-expert C++ developers on idiomatic code and methods

Help ensure our codebase is structured for effective use with AI-assisted development tools

Write clear, self-documenting code with consistent conventions, meaningful naming, and well-organized modules

Learn about the state of the art in SoC IP and chip-level architecture

Work on data analysis pipelines, visualization methodologies, continuous regression testing

Run performance simulations

We are seeking an upbeat and highly motivated SOC Performance Modeling SW Engineer to work on our performance models and infrastructure., MS or PhD in CS, EE or related field

10+ years of relevant experience

Experience with multi-paradigm software development in C++

Experience with multi-language programming environments, and selecting the right tool or language for the job

Experience with compiler explorer and understanding the transformations the compiler is performing on your code

Experience thinking about code as something that will be read by both humans and machines, and instituting conventions, structure, and documentation that make a codebase tractable for AI-assisted reasoning and navigation

Experience with architectural, micro-architectural performance modeling

Minimum Qualifications

Bachelor’s degree

Experience in hardware architecture and design issues

Experience coding in C++ and Python

Experience with computer architecture and software engineering principles

Experience with data structures and algorithms

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish! Join us to help deliver the next groundbreaking Apple product.

In this role, you will be a member of the system-on-chip (SOC) performance team, working within the Hardware Technologies organization to shape the architecture of Apple’s future devices. Our team initiates and fosters deep collaboration between the SOC architecture, design, power, and software teams, to deliver world-class caches/memory system. The end goal is to provide the best customer experience in the world by enabling all the CPUs, GPUs, Machine Learning, Camera, Display, and Connectivity components on our chips to work seamlessly together.