FPGA Engineer

IC Resources
Delft, Netherlands
3 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
5 years minimum
Compensation
€5,833.0 - €7,083.0
Working hours
Regular working hours

Tech stack

C++ (Programming Language) Microarchitecture Linux Logic Synthesis of Circuits Embedded Software Field-Programmable Gate Array (FPGA) Python (Programming Language) Software Architecture System on a Chip SystemVerilog Tcl (Programming Language) VHSIC Hardware Description Language (VHDL)
+3 more
Vivado Scripting Git

Job description

Help solve the hardware challenges involved in controlling quantum computers at industrial scale. We are supporting a quantum technology company developing advanced control systems used by research and engineering teams around the world. They are looking for a Senior FPGA Engineer to strengthen their digital design team in Delft.

Requirements

At the heart of the position is a distributed FPGA architecture capable of controlling and reading out large numbers of qubits with nanosecond-level synchronisation. You’ll take ownership of complex design problems, influence architectural decisions, and collaborate with FPGA, embedded software, electronics, and scientific teams. From interpreting requirements through to verification, you’ll develop RTL in VHDL, create self-checking testbenches, contribute to wider UVM environments, and help continuously improve FPGA architectures and engineering processes. They are looking for a Senior FPGA Engineer with the following background:

  • 5+ years of FPGA design experience within an R&D environment
  • Strong RTL development using VHDL
  • Experience with Xilinx Vivado or Intel Quartus
  • Strong module-level verification experience
  • Knowledge of simulation tools such as QuestaSim
  • Understanding of processor and bus architectures including AXI or Avalon
  • Scripting experience with Python, TCL or Shell
  • Experience with Git-based development

Experience with Zynq, UltraScale+, RFSoC, SystemVerilog, UVM, DSP, timing closure, C/C++, Linux, or microarchitecture design would be advantageous.

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