Sr. Staff Engineer - Digital Design Verification

Company OverviewAmbiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world’s lowest-power semiconductor solutions.Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we’ve shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.We’re looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.If that’s you, join us - the intelligence everywhere revolution starts here.ResponsibilitiesYou will be responsible for verifying complex digital designs, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.The ideal candidate is a self-starter who takes full ownership of verification efforts and consistently delivers high-quality, production-ready silicon.Key responsibilities include:Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levelsDevelop detailed verification plans aligned with architecture and design specificationsPerform SoC-level verification using full-chip simulation and regression environmentsArchitect and implement scalable, reusable UVM-based testbenches using SystemVerilogDevelop comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverageDrive constrained-random and directed testing, including scoreboarding and self-checking mechanismsDevelop and maintain C/C++ based verification libraries and tests for SoC-level validationAutomate verification flows for regressions, coverage collection, and results reportingDefine, track, and close functional and code coverage goalsUtilize advanced debugging methodologies to isolate and resolve complex design and verification issuesPerform root-cause analysis and collaborate closely with design teams to drive fixesEnsure verification quality meets or exceeds project, schedule, and industry standardsExperience with edge-based AI inference workloads is a plus.RequirementsBSEE or MSEE with 8-12 years of hands-on digital design verification experienceProven track record of multiple tape-outs with silicon functioning to specificationStrong experience in block-level, sub-system, and full-chip SoC verificationAbility to define and manage verification deliverables, milestones, and schedulesProactively identify verification risks and implement mitigation strategiesExperience working with complex SoCs integrating multiple 3rd-party IPs and VIPsStrong collaboration skills to work effectively with design, architecture, and software teamsExcellent communication skills for reporting status, issues, and progress to stakeholdersTechnical SkillsDesign Verification:SystemVerilog, UVM, VerilogFunctional and code coverage methodologiesConstrained-random verification and scoreboardingSoC & Software-Based Verification:C/C++ based verification in SoC environments (required)Experience with processor-based systems (ARM and/or RISC-V preferred)Architectures & Protocols:ARM or RISC-V processor-based SoCsAMBA protocols (AXI, AHB, APB)DMA, flow control, and standard serial interfacesScripting & Automation:Python, Perl, MakefileLow Power (Digital):Experience verifying low-power digital architectures and features is highly desirablePreferred ExperienceSecurity IPs (Crypto, OTP)DSP and compute-heavy digital subsystemsHigh-performance or low-power SoC architecturesEdge AI / ML workload enablementMust be currently authorized to work in the United States for any employer. Company OverviewAmbiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world’s lowest-power semiconductor solutions.Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we’ve shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.We’re looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.If that’s you, join us - the intelligence everywhere revolution starts here.ResponsibilitiesYou will be responsible for verifying complex digital designs, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.The ideal candidate is a self-starter who takes full ownership of verification efforts and consistently delivers high-quality, production-ready silicon.Key responsibilities include:Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levelsDevelop detailed verification plans aligned with architecture and design specificationsPerform SoC-level verification using full-chip simulation and regression environmentsArchitect and implement scalable, reusable UVM-based testbenches using SystemVerilogDevelop comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverageDrive constrained-random and directed testing, including scoreboarding and self-checking mechanismsDevelop and maintain C/C++ based verification libraries and tests for SoC-level validationAutomate verification flows for regressions, coverage collection, and results reportingDefine, track, and close functional and code coverage goalsUtilize advanced debugging methodologies to isolate and resolve complex design and verification issuesPerform root-cause analysis and collaborate closely with design teams to drive fixesEnsure verification quality meets or exceeds project, schedule, and industry standardsExperience with edge-based AI inference workloads is a plus.RequirementsBSEE or MSEE with 8-12 years of hands-on digital design verification experienceProven track record of multiple tape-outs with silicon functioning to specificationStrong experience in block-level, sub-system, and full-chip SoC verificationAbility to define and manage verification deliverables, milestones, and schedulesProactively identify verification risks and implement mitigation strategiesExperience working with complex SoCs integrating multiple 3rd-party IPs and VIPsStrong collaboration skills to work effectively with design, architecture, and software teamsExcellent communication skills for reporting status, issues, and progress to stakeholdersTechnical SkillsDesign Verification:SystemVerilog, UVM, VerilogFunctional and code coverage methodologiesConstrained-random verification and scoreboardingSoC & Software-Based Verification:C/C++ based verification in SoC environments (required)Experience with processor-based systems (ARM and/or RISC-V preferred)Architectures & Protocols:ARM or RISC-V processor-based SoCsAMBA protocols (AXI, AHB, APB)DMA, flow control, and standard serial interfacesScripting & Automation:Python, Perl, MakefileLow Power (Digital):Experience verifying low-power digital architectures and features is highly desirablePreferred ExperienceSecurity IPs (Crypto, OTP)DSP and compute-heavy digital subsystemsHigh-performance or low-power SoC architecturesEdge AI / ML workload enablementMust be currently authorized to work in the United States for any employer. Company OverviewAmbiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world’s lowest-power semiconductor solutions.Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we’ve shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.We’re looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.If that’s you, join us - the intelligence everywhere revolution starts here. ResponsibilitiesYou will be responsible for verifying complex digital designs, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.The ideal candidate is a self-starter who takes full ownership of verification efforts and consistently delivers high-quality, production-ready silicon.Key responsibilities include:Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levelsDevelop detailed verification plans aligned with architecture and design specificationsPerform SoC-level verification using full-chip simulation and regression environmentsArchitect and implement scalable, reusable UVM-based testbenches using SystemVerilogDevelop comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverageDrive constrained-random and directed testing, including scoreboarding and self-checking mechanismsDevelop and maintain C/C++ based verification libraries and tests for SoC-level validationAutomate verification flows for regressions, coverage collection, and results reportingDefine, track, and close functional and code coverage goalsUtilize advanced debugging methodologies to isolate and resolve complex design and verification issuesPerform root-cause analysis and collaborate closely with design teams to drive fixesEnsure verification quality meets or exceeds project, schedule, and industry standardsExperience with edge-based AI inference workloads is a plus.RequirementsBSEE or MSEE with 8-12 years of hands-on digital design verification experienceProven track record of multiple tape-outs with silicon functioning to specificationStrong experience in block-level, sub-system, and full-chip SoC verificationAbility to define and manage verification deliverables, milestones, and schedulesProactively identify verification risks and implement mitigation strategiesExperience working with complex SoCs integrating multiple 3rd-party IPs and VIPsStrong collaboration skills to work effectively with design, architecture, and software teamsExcellent communication skills for reporting status, issues, and progress to stakeholdersTechnical SkillsDesign Verification:SystemVerilog, UVM, VerilogFunctional and code coverage methodologiesConstrained-random verification and scoreboardingSoC & Software-Based Verification:C/C++ based verification in SoC environments (required)Experience with processor-based systems (ARM and/or RISC-V preferred)Architectures & Protocols:ARM or RISC-V processor-based SoCsAMBA protocols (AXI, AHB, APB)DMA, flow control, and standard serial interfacesScripting & Automation:Python, Perl, MakefileLow Power (Digital):Experience verifying low-power digital architectures and features is highly desirablePreferred ExperienceSecurity IPs (Crypto, OTP)DSP and compute-heavy digital subsystemsHigh-performance or low-power SoC architecturesEdge AI / ML workload enablementMust be currently authorized to work in the United States for any employer. ResponsibilitiesYou will be responsible for verifying complex digital designs, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.The ideal candidate is a self-starter who takes full ownership of verification efforts and consistently delivers high-quality, production-ready silicon.Key responsibilities include:Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levelsDevelop detailed verification plans aligned with architecture and design specificationsPerform SoC-level verification using full-chip simulation and regression environmentsArchitect and implement scalable, reusable UVM-based testbenches using SystemVerilogDevelop comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverageDrive constrained-random and directed testing, including scoreboarding and self-checking mechanismsDevelop and maintain C/C++ based verification libraries and tests for SoC-level validationAutomate verification flows for regressions, coverage collection, and results reportingDefine, track, and close functional and code coverage goalsUtilize advanced debugging methodologies to isolate and resolve complex design and verification issuesPerform root-cause analysis and collaborate closely with design teams to drive fixesEnsure verification quality meets or exceeds project, schedule, and industry standardsExperience with edge-based AI inference workloads is a plus.RequirementsBSEE or MSEE with 8-12 years of hands-on digital design verification experienceProven track record of multiple tape-outs with silicon functioning to specificationStrong experience in block-level, sub-system, and full-chip SoC verificationAbility to define and manage verification deliverables, milestones, and schedulesProactively identify verification risks and implement mitigation strategiesExperience working with complex SoCs integrating multiple 3rd-party IPs and VIPsStrong collaboration skills to work effectively with design, architecture, and software teamsExcellent communication skills for reporting status, issues, and progress to stakeholdersTechnical SkillsDesign Verification:SystemVerilog, UVM, VerilogFunctional and code coverage methodologiesConstrained-random verification and scoreboardingSoC & Software-Based Verification:C/C++ based verification in SoC environments (required)Experience with processor-based systems (ARM and/or RISC-V preferred)Architectures & Protocols:ARM or RISC-V processor-based SoCsAMBA protocols (AXI, AHB, APB)DMA, flow control, and standard serial interfacesScripting & Automation:Python, Perl, MakefileLow Power (Digital):Experience verifying low-power digital architectures and features is highly desirablePreferred ExperienceSecurity IPs (Crypto, OTP)DSP and compute-heavy digital subsystemsHigh-performance or low-power SoC architecturesEdge AI / ML workload enablement ResponsibilitiesYou will be responsible for verifying complex digital designs, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.The ideal candidate is a self-starter who takes full ownership of verification efforts and consistently delivers high-quality, production-ready silicon.Key responsibilities include:Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levelsDevelop detailed verification plans aligned with architecture and design specificationsPerform SoC-level verification using full-chip simulation and regression environmentsArchitect and implement scalable, reusable UVM-based testbenches using SystemVerilogDevelop comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverageDrive constrained-random and directed testing, including scoreboarding and self-checking mechanismsDevelop and maintain C/C++ based verification libraries and tests for SoC-level validationAutomate verification flows for regressions, coverage collection, and results reportingDefine, track, and close functional and code coverage goalsUtilize advanced debugging methodologies to isolate and resolve complex design and verification issuesPerform root-cause analysis and collaborate closely with design teams to drive fixesEnsure verification quality meets or exceeds project, schedule, and industry standardsExperience with edge-based AI inference workloads is a plus.RequirementsBSEE or MSEE with 8-12 years of hands-on digital design verification experienceProven track record of multiple tape-outs with silicon functioning to specificationStrong experience in block-level, sub-system, and full-chip SoC verificationAbility to define and manage verification deliverables, milestones, and schedulesProactively identify verification risks and implement mitigation strategiesExperience working with complex SoCs integrating multiple 3rd-party IPs and VIPsStrong collaboration skills to work effectively with design, architecture, and software teamsExcellent communication skills for reporting status, issues, and progress to stakeholdersTechnical SkillsDesign Verification:SystemVerilog, UVM, VerilogFunctional and code coverage methodologiesConstrained-random verification and scoreboardingSoC & Software-Based Verification:C/C++ based verification in SoC environments (required)Experience with processor-based systems (ARM and/or RISC-V preferred)Architectures & Protocols:ARM or RISC-V processor-based SoCsAMBA protocols (AXI, AHB, APB)DMA, flow control, and standard serial interfacesScripting & Automation:Python, Perl, MakefileLow Power (Digital):Experience verifying low-power digital architectures and features is highly desirablePreferred ExperienceSecurity IPs (Crypto, OTP)DSP and compute-heavy digital subsystemsHigh-performance or low-power SoC architecturesEdge AI / ML workload enablement ResponsibilitiesYou will be responsible for verifying complex digital designs, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.The ideal candidate is a self-starter who takes full ownership of verification efforts and consistently delivers high-quality, production-ready silicon.Key responsibilities include:Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levelsDevelop detailed verification plans aligned with architecture and design specificationsPerform SoC-level verification using full-chip simulation and regression environmentsArchitect and implement scalable, reusable UVM-based testbenches using SystemVerilogDevelop comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverageDrive constrained-random and directed testing, including scoreboarding and self-checking mechanismsDevelop and maintain C/C++ based verification libraries and tests for SoC-level validationAutomate verification flows for regressions, coverage collection, and results reportingDefine, track, and close functional and code coverage goalsUtilize advanced debugging methodologies to isolate and resolve complex design and verification issuesPerform root-cause analysis and collaborate closely with design teams to drive fixesEnsure verification quality meets or exceeds project, schedule, and industry standardsExperience with edge-based AI inference workloads is a plus.RequirementsBSEE or MSEE with 8-12 years of hands-on digital design verification experienceProven track record of multiple tape-outs with silicon functioning to specificationStrong experience in block-level, sub-system, and full-chip SoC verificationAbility to define and manage verification deliverables, milestones, and schedulesProactively identify verification risks and implement mitigation strategiesExperience working with complex SoCs integrating multiple 3rd-party IPs and VIPsStrong collaboration skills to work effectively with design, architecture, and software teamsExcellent communication skills for reporting status, issues, and progress to stakeholdersTechnical SkillsDesign Verification:SystemVerilog, UVM, VerilogFunctional and code coverage methodologiesConstrained-random verification and scoreboardingSoC & Software-Based Verification:C/C++ based verification in SoC environments (required)Experience with processor-based systems (ARM and/or RISC-V preferred)Architectures & Protocols:ARM or RISC-V processor-based SoCsAMBA protocols (AXI, AHB, APB)DMA, flow control, and standard serial interfacesScripting & Automation:Python, Perl, MakefileLow Power (Digital):Experience verifying low-power digital architectures and features is highly desirablePreferred ExperienceSecurity IPs (Crypto, OTP)DSP and compute-heavy digital subsystemsHigh-performance or low-power SoC architecturesEdge AI / ML workload enablement Must be currently authorized to work in the United States for any employer. Must be currently authorized to work in the United States for any employer. Must be currently authorized to work in the United States for any employer.

We’re looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency., * BSEE or MSEE with 8-12 years of hands-on digital design verification experience

• Proven track record of multiple tape-outs with silicon functioning to specification
• Strong experience in block-level, sub-system, and full-chip SoC verification
• Ability to define and manage verification deliverables, milestones, and schedules
• Proactively identify verification risks and implement mitigation strategies
• Experience working with complex SoCs integrating multiple 3rd-party IPs and VIPs
• Strong collaboration skills to work effectively with design, architecture, and software teams
• Excellent communication skills for reporting status, issues, and progress to stakeholders

Technical Skills

• Design Verification:
• SystemVerilog, UVM, Verilog
• Functional and code coverage methodologies
• Constrained-random verification and scoreboarding
• SoC & Software-Based Verification:
• C/C++ based verification in SoC environments (required)
• Experience with processor-based systems (ARM and/or RISC-V preferred)
• Architectures & Protocols:
• ARM or RISC-V processor-based SoCs
• AMBA protocols (AXI, AHB, APB)
• DMA, flow control, and standard serial interfaces
• Scripting & Automation:
• Python, Perl, Makefile
• Low Power (Digital):
• Experience verifying low-power digital architectures and features is highly desirable

Preferred Experience

• Security IPs (Crypto, OTP)
• DSP and compute-heavy digital subsystems
• High-performance or low-power SoC architectures
• Edge AI / ML workload enablement

Must be currently authorized to work in the United States for any employer.

Ambiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world’s lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we’ve shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.