Senior Logic Design Engineer

The candidate for this position will be expected and able to complete the following responsibilities: Design, develop, and maintain robust timing (SDC) constraints ensuring functional correctness, hierarchical consistency, and tool compatibility while enabling PPA targets. Leverage state of the art tools to generate constraints and perform quality assurance for PD and STA consumption. Collaborate and support Physical Design, STA, and DFT teams with collaterals from initial RTL handoff to tape out. Analyze and debug synthesis results to drive RTL optimization towards achieving PPA targets Automate tasks using scripting for efficiency Utilize AI for gaining efficiency within process and development Continue to grow your micro-architectural knowledge and contribute to unit, sub-system and SOC micro-architecture Development and integration of various functional block RTL Perform design quality checks such as Timing closure, Lint, CDC, Synthesis, Low Power Intent Exercise the functionality of

the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary. Delight your customers by providing high-quality functional blocks on schedule and with professional integrity Challenge the status quo with growth mindset. Mentor team members and summer interns for a growing team Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Experience in static timing analysis and logic domain including SDC/Timing Constraint generation, analysis, and quality assurance. Experience with synthesis script setup, debug, analysis, and drive to quality targets. Knowledge of logic design flow including Low Power Analysis, UPF, RTL coding, Synthesis, timing constraints, timing closure. Demonstrated expertise in Computer Architecture, Digital Design, IP/SoC design principles as part of SoC and/or IP development. Highly Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (VCLP, Verilog simulators, Connectivity tools, low power static checkers, linting) Demonstrated experience and knowledge of clock crossings, and power/UPF in design Ability to write scripts using Perl, Tcl, Python etc. Familiarity with Industry standard interface protocols (ARM) is a plus. Familiarity with Formal Equivalence Verification and Power Analysis is a plus. Verbal and written communication skills.