job summary: Seeking a Senior ASIC Technical Lead for a high growth industrial capital equipment development and manufacturing client in the Agoura Hills, CA area.

The Senior ASIC Technical Lead would be responsible for drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment (ATE) systems. This role requires a proven leader who can drive complex ASIC programs from concept through production, coordinating cross-functional engineering teams, external partners, and key stakeholders while ensuring successful execution against technical, schedule, cost, and quality objectives.

Experience with analog ASIC Engineering and project functional management is required, including driving schedules/budgets, working with vendors, managing deliverables and corrective actions as required.

Full W2 Benefits offered including, profit sharing, bonus and stock options! APPLY NOW!

location: Agoura Hills, California job type: Permanent salary: $240,000 - 280,000 per year work hours: 9am to 5pm education: Bachelors

responsibilities: Execution & Delivery: Directed end-to-end ASIC execution from concept to production, driving tapeout readiness, silicon bring-up, and first-pass success on time and within budget.

Team Leadership: Led cross-functional teams spanning architecture, analog/digital design, verification, physical design, packaging, test, and operations.

Strategic Alignment: Partnered with system architects and engineering leaders to define architecture, technical trade-offs, product requirements, and execution strategy.

Program Management: Managed schedule development, critical paths, milestone tracking, risk mitigation, and executive status reporting.

Vendor & Partner Management: Coordinated external design partners, EDA vendors, IP suppliers, and foundry operations.

Resource Management: Developed staffing plans and resolved resource gaps across all project lifecycles.

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qualifications: BSEE, MSEE, or equivalent with 15+ years of related industry experience and 5+ years leading complex ASIC developments.

Demonstrated success leading multiple complex mixed-signal ASICs through architecture, design, verification, tapeout, silicon bring-up, and production.

Experience managing geographically distributed teams and external design partners.

Strong program management skills, including schedule planning, risk management, and executive communications.

Proven ability to lead through influence across multiple engineering disciplines.

Experience with advanced-node ASIC development preferred.

skills: ASIC,digital design,physical design,Communication,coordinating,Coordinate,leadership,ability to lead,passion,determination,Accountable,architecture,Automated Test Equipment,customer success,analog design,mixed-signal,foundry,package engineering,Partner Management,product requirements,program management,milestone tracking,risk,risk management,schedule development,schedule planning,semiconductor industry,technical depth

Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact HRsupport@randstadusa.com.

Pay offered to a successful candidate will be based on several factors including the candidate’s education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad offers a comprehensive benefits package, including: medical, prescription, dental, vision, AD&D, and life insurance offerings, short-term disability, and a 401K plan (all benefits are based on eligibility).

This posting is open for thirty (30) days.

Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance.

Qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.

We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles’ Fair Chance Initiative for Hiring Ordinance.

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Execution & Delivery: Directed end-to-end ASIC execution from concept to production, driving tapeout readiness, silicon bring-up, and first-pass success on time and within budget.

Team Leadership: Led cross-functional teams spanning architecture, analog/digital design, verification, physical design, packaging, test, and operations.

Strategic Alignment: Partnered with system architects and engineering leaders to define architecture, technical trade-offs, product requirements, and execution strategy.

Program Management: Managed schedule development, critical paths, milestone tracking, risk mitigation, and executive status reporting.

Vendor & Partner Management: Coordinated external design partners, EDA vendors, IP suppliers, and foundry operations.

Resource Management: Developed staffing plans and resolved resource gaps across all project lifecycles.

LI-JM1

ASIC,digital design,physical design,Communication,coordinating,Coordinate,leadership,ability to lead,passion,determination,Accountable,architecture,Automated Test Equipment,customer success,analog design,mixed-signal,foundry,package engineering,Partner Management,product requirements,program management,milestone tracking,risk,risk management,schedule development,schedule planning,semiconductor industry,technical depth