ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration
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Role details
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Job description
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team youāll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; weāre handling massive scale and rapid integration of emergent technologies. Weāre looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.
Requirements
n- 3+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience\n \nPREFERRED QUALIFICATIONS- Masterās degree in computer science or equivalent\n \n- 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience\n
Benefits & conditions
n \n \nKey job responsibilities\n \nAs an ASIC Design Engineer, you will:\n \n \n* Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets\n \n \n* Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements\n \n \n* Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints\n \n \n* Execute lint and clock domain crossing quality checks to ensure design integrity\n \n \n* Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts\n \n \nThe ideal candidate will have a strong background in ASIC design, proficiency in SystemVerilog, and excellent analytical and problem-solving skills. Experience with high-performance and power-efficient designs is highly desirable.\n \n \n \nYou will thrive in this role if you:\n \n- Have a āLearn and Be Curiousā mindset\n \n- Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures\n \n- Have a strong drive to innovate, explore new solutions, and contribute to the companyās intellectual property through patents\n \n \nAbout the team\n \nInclusive Team Culture\n \nHere at AWS, we embrace our differences. We are committed to furthering our culture of inclusion. We have ten employee-led affinity groups, reaching 40,000 employees in over 190 chapters globally. We have innovative benefit offerings, and host annual and ongoing learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon conferences. Amazonās culture of inclusion is reinforced within our 16 Leadership Principles, which remind team members to seek diverse perspectives, learn and be curious, and earn trust.\n \n \nWork/Life Balance\n \nOur team puts a high value on work-life balance. It isnāt about how many hours you spend at home or at work; itās about the flow you establish that brings energy to both parts of your life. We believe striking the right balance between your personal and professional life is critical to life-long happiness and fulfillment. We offer flexibility in working hours and encourage you to find your own balance between your work and personal lives.\n \n \nMentorship & Career Growth\n \nOur team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and weāre building an environment that celebrates knowledge sharing and mentorship. We care about your career growth and strive to assign projects based on what will help each team member develop into a better-rounded professional and enable them to take on more complex tasks in the future.\n
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