ASIC Engineer, EDA Infrastructure

1. Front End implementation flow development and support
2. Physical Design implementation flow development and support
3. RTL2GDS flow development and support
4. Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation
5. Work with EDA vendors on new tools/technology and new features evaluation and adoption
6. Manage the internal EDA license requests, installation and license forecast as well as EDA tool installation and maintenance
7. Work with internal infrastructure team on compute grid, storage management and job scheduling architecture, efficiency and maintenance
8. Work with internal infrastructure team on adapting internal infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management and reporting

Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. We are looking for individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build System on Chip (SoC) and IP for data center applications., 1. Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta

1. Bachelor’s degree in Computer Science, Electrical Engineering, or Computer Engineering, in a relevant technical field, or equivalent practical experience
2. 2+ years of experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments
3. Experience with ASIC EDA infrastructure (compute, storage, job scheduling) management, maintenance and support
4. Experience with developing and supporting solutions for ASIC design environment and infrastructure
5. Experience with communicating across functional internal teams and with vendors, 1. Experience designing tools and workflows with a focus on usability and end-user productivity
6. Knowledge of front-end and back-end ASIC tools and flows
7. Experience setting up EDA infrastructure from scratch
8. Experience with RTL design using SystemVerilog or other HDL