Performance Modelling Engineer - Mid

Hireroo Ltd
Málaga, Spain
6 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience required
2 years minimum
Working hours
Regular working hours

Tech stack

Data Analysis Automation of Tests Bash Shell C++ (Programming Language) Profiling Linux Field-Programmable Gate Array (FPGA) Python (Programming Language) PCI Express Tcl (Programming Language) Perf (Linux)

Job description

Job Description Our partner is looking for a Performance Modelling Engineer to work on performance analysis and modelling for advanced compute systems.The role focuses on simulator instrumentation, workload analysis, cycle accurate modelling and connecting software behaviour with hardware events.You will take ownership of assigned components from analysis through validation and sign off.Location: Barcelona, Spain, HybridLevel: Mid Responsibilities Build and validate performance models Instrument simulators and collect performance counters Analyze workloads and correlate software behaviour with hardware events Build repeatable performance test environments Profile applications and visualize execution behaviour Support cycle accurate and analytical modelling Work with architecture and software teams Identify tooling and methodology gaps Own assigned components from specification to sign off Contribute to technical reviews and performance decisions Requirements Around 2 to 5 years of relevant experience Strong C/C++ Python, Bash or Tcl Linux Profiling tools such as perf, VTune, Nsight Systems, Perfetto, Intel Advisor or FlameGraph Simulator instrumentation and performance counter analysis RISC V instruction level analysis Strong understanding of xPU architecture, pipelines and memory behaviour PCIe and basic multi xPU or multi node topology knowledge Cycle accurate simulators or analytical modelling Understanding of RTL, software, FPGA and silicon validation Experience with scaled test automation, tracing and data analysis Optional / Desired RISC V Vector assembly RTL design and simulation Roofline modelling Kernel and call stack profiling Trace based analysis Silicon lifecycle knowledge JIT, event based or cycle based modelling Architecture based optimization PhD in a relevant technical field What’s in it for you?Flexible working hours Hybrid model, 4 days office, 1 day from home 1 week per year working from anywhere 25 days annual leave plus December 24 and 31 Monthly food allowance Private medical insurance Relocation bonus Housing search support Visa support if required Family relocation support Virtual shares Language classes Tax incentive, subject to eligibility #J-*****-Ljbffr

Requirements

The role focuses on simulator instrumentation, workload analysis, cycle accurate modelling and connecting software behaviour with hardware events. You will take ownership of assigned components from analysis through validation and sign off. Location: Barcelona, Spain, HybridLevel: Mid Responsibilities Build and validate performance models Instrument simulators and collect performance counters Analyze workloads and correlate software behaviour with hardware events Build repeatable performance test environments Profile applications and visualize execution behaviour Support cycle accurate and analytical modelling Work with architecture and software teams Identify tooling and methodology gaps Own assigned components from specification to sign off Contribute to technical reviews and performance decisions Requirements Around 2 to 5 years of relevant experience Strong C/C++ Python, Bash or Tcl Linux Profiling tools such as perf, VTune, Nsight Systems, Perfetto, Intel Advisor or FlameGraph Simulator instrumentation and performance counter analysis RISC V instruction level analysis Strong understanding of xPU architecture, pipelines and memory behaviour PCIe and basic multi xPU or multi node topology knowledge Cycle accurate simulators or analytical modelling Understanding of RTL, software, FPGA and silicon validation Experience with scaled test automation, tracing and data analysis Optional / Desired RISC V Vector assembly RTL design and simulation Roofline modelling Kernel and call stack profiling Trace based analysis Silicon lifecycle knowledge JIT, event based or cycle based modelling Architecture based optimization PhD in a relevant technical field What’s in it for you? Flexible working hours Hybrid model, 4 days office, 1 day from home 1 week per year working from anywhere 25 days annual leave plus December 24 and 31 Monthly food allowance Private medical insurance Relocation bonus Housing search support Visa support if required Family relocation support Virtual shares Language classes Tax incentive, subject to eligibility #J-*****-Ljbffr

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