Senior Firmware Engineer

Donatech Corporation
Cedar Rapids, IA, United States
9 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
4 years minimum
Compensation
$150,800.0 - $171,600.0
Working hours
Regular working hours
Job source

Tech stack

Systems Engineering Digital Electronics Firmware Field-Programmable Gate Array (FPGA) Requirements Management Verification and Validation (Software) Static Timing Analysis Subversion SystemVerilog Verilog VHSIC Hardware Description Language (VHDL) Vivado
+4 more
Fpga Hardware ModelSim Git Software Version Control

Job description

  • Requirements Management: Developing, reviewing, and maintaining hardware requirements to ensure completeness, correctness, and traceability to system-level requirements in DOORS.
  • Design and Implementation: Creating complex hardware designs, often using FPGAs, that meet DAL A objectives.
  • Verification and Validation: Performing rigorous verification activities, including functional testing, quantitative analysis, and reviews, to demonstrate that the hardware meets all requirements
  • Tool Assessment: Evaluating and qualifying design and verification tools to ensure they do not introduce errors, especially for Level A hardware
  • Documentation and Compliance: Maintaining detailed records of design decisions, verification results, and traceability matrices to satisfy certification authorities
  • Cross-Functional Collaboration: Working closely with systems engineers, software teams, and certification authorities to ensure integrated system safety.

Requirements

Proven experience in FPGA development and DO-254 compliance processes. Familiarity with DO-254 DAL A, Mil-516C related certification guidance. Expertise in verification planning, testing, and tool qualification. Ability to produce thorough documentation and maintain traceability from requirements to implementation and verification.

  • RTL coding and simulation in VHDL or Verilog
  • Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
  • Testbench development for the verification of RTL blocks using VHDL or System Verilog.
  • Proficiency using FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
  • Familiarity with revision control concepts and tools (e.g. Git, Subversion)
  • Ability to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones.
  • Strong oral and written communication skills with the ability to document and present one’s work and status
  • Bachelor’s Degree in applicable engineering or science field plus 4 years related experience.

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