Staff System Achitect

You will work with architects and engineering teams to turn requirements into efficient digital hardware, balancing performance, power and area. The role also offers scope to explore AI-assisted tools and automation that improve design, verification and implementation workflows., * Design, develop and maintain synthesizable RTL using SystemVerilog or Verilog.

• Translate architectural and functional requirements into efficient hardware implementations.
• Develop verification environments, including testbenches, and perform functional verification.
• Integrate digital IP blocks and subsystems, including interfaces, control logic and datapaths.
• Partner with system architects and engineering teams to evaluate performance, power and area trade-offs.
• Debug, optimise and integrate RTL, and use synthesis results to assess implementation outcomes.
• Improve hardware development workflows through automation and exploration of AI-assisted tooling., You will work on technically challenging hardware platforms and subsystems, with the opportunity to contribute across design, verification and implementation. You will collaborate with architects and engineers on meaningful trade-offs and help shape practical improvements to the way hardware is developed.

This role offers scope to deepen your technical expertise, explore emerging tools and approaches, and make an impact through high-quality engineering and continuous improvement., Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

• Experience designing and verifying synthesizable RTL using SystemVerilog or Verilog.
• Ability to develop and maintain testbenches and investigate functional verification issues.
• Experience using synthesis to evaluate RTL implementation results and support gate-level builds.
• Ability to analyse technical problems, communicate design decisions clearly and collaborate across engineering disciplines.

Nice-to-Have Skills and Experience

• Experience with FPGA build and implementation.
• Familiarity with AI-assisted tools or automation for hardware design, verification or synthesis workflows.
• Knowledge of advanced verification methodologies and tools.
• Experience improving engineering processes, build methodologies or development automation.