Senior ASIC Design Engineer - AI Accelerator / SoC

1. ASIC Microarchitecture and RTL Design * Develop detailed microarchitecture specifications based on system-level and functional requirements. * Design and implement complex digital logic using Verilog/SystemVerilog. * Develop high-performance datapaths, control logic, finite state machines, arbitration mechanisms, and communication interfaces. * Implement efficient pipelining, buffering, flow control, and resource-sharing mechanisms. * Optimize RTL designs for timing, power consumption, silicon area, and implementation feasibility. * Perform RTL code reviews, design analysis, and functional debugging. * Collaborate with architecture engineers to evaluate design trade-offs and improve subsystem performance.

2. AI Accelerator and SoC Subsystem Design * Design and implement functional blocks and subsystems for AI accelerators, GPU, NPU, or complex SoC architectures. * Develop compute pipelines, memory interfaces, DMA engines, on-chip interconnects, and data movement logic. * Understand and implement hardware mechanisms supporting parallel computation, high-throughput processing, and efficient memory access. * Optimize data movement, memory bandwidth utilization, latency, and overall subsystem performance. * Collaborate with system architects and algorithm engineers to translate computational requirements into efficient hardware implementations.

3. Memory and High-Speed Interface Integration * Design and integrate memory controllers, on-chip interconnects, and high-speed interface subsystems. * Work with memory subsystem architectures, including memory arbitration, buffering, transaction ordering, and data flow control. * Support integration of standard interfaces such as AMBA AXI and other SoC interconnect protocols. * Collaborate with IP and system integration teams to ensure functional correctness and interface compatibility. * Analyze interface performance, bandwidth utilization, and latency bottlenecks.

4. ASIC Development and Design Implementation * Participate in the ASIC development lifecycle from specification and microarchitecture through RTL design, verification, synthesis, physical implementation, and tape-out. * Develop synthesizable, maintainable, and production-quality RTL that meets design requirements. * Perform lint checks, clock-domain crossing (CDC) analysis, and reset-domain crossing (RDC) analysis. * Support logic synthesis, static timing analysis, and timing closure. * Work with physical design engineers to address timing, congestion, power, and area challenges. * Analyze and resolve functional and implementation issues identified during simulation, synthesis, and physical design. * Support silicon bring-up, post-silicon debugging, and validation activities as needed.

5. Functional Verification and Hardware/Software Integration * Collaborate with verification engineers to develop functional verification plans and test scenarios. * Support IP-level and SoC-level verification, including simulation, debugging, and regression analysis. * Analyze simulation failures and debug RTL functional issues using waveforms, logs, and assertions. * Participate in hardware/software interface definition, including control/status registers, interrupts, and programming models. * Support FPGA prototyping, emulation, and hardware/software integration testing. * Work with firmware and software engineers to resolve system-level functional issues.

The ideal candidate will have strong hands-on experience in digital ASIC design, with a solid understanding of GPU, NPU, or complex SoC subsystem architectures. The candidate should be proficient in translating functional specifications into detailed microarchitecture and synthesizable RTL, optimizing designs for performance, power, and area (PPA), and supporting the complete ASIC development lifecycle., * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 5+ years of hands-on experience in digital ASIC/SoC design, microarchitecture, and RTL implementation.
• Strong architecture and microarchitecture knowledge, with hands-on design experience in at least one of the following:
• GPU or parallel computing architectures
• NPU, AI accelerator, or machine learning processor architectures
• Complex SoC subsystems, such as memory controllers, interconnect fabrics, DMA engines, or high-performance processing subsystems
• Strong proficiency in Verilog/SystemVerilog RTL design.
• Experience translating functional specifications into microarchitecture specifications and synthesizable RTL.
• Solid understanding of digital logic design, pipelining, finite state machines, datapaths, memory systems, and on-chip interconnect architectures.
• Experience with RTL simulation, debugging, synthesis, lint, and static timing analysis.
• Familiarity with clock-domain crossing (CDC), reset design, and timing constraints.
• Experience working with verification engineers to debug functional issues and achieve design correctness.
• Understanding of ASIC design flow from specification through synthesis, physical implementation, and tape-out.
• Strong analytical, debugging, and problem-solving skills.
• Ability to independently design, implement, and debug complex ASIC functional blocks., * Direct design experience with GPU, NPU, AI accelerator, or heterogeneous computing SoCs.
• Knowledge of chip-to-chip and die-to-die interconnect technologies, including UCIe (Universal Chiplet Interconnect Express) or other high-speed interconnect protocols.
• Knowledge of LPDDR memory technologies, particularly LPDDR5/LPDDR5X and LPDDR6, including memory controller architecture and interface integration.
• Knowledge of PCIe, particularly PCIe Gen5/Gen6, including controller architecture, transaction processing, and subsystem integration.
• Familiarity with NoC architectures, cache coherency, memory consistency, and high-bandwidth data movement.
• Experience with AMBA AXI/ACE/CHI or other industry-standard SoC interconnect protocols.
• Understanding of AI/ML workloads, including matrix multiplication, tensor operations, and inference acceleration.
• Experience with hardware/software co-design, firmware interfaces, or system-level integration.
• Familiarity with UVM-based functional verification, SystemVerilog Assertions (SVA), or formal verification.
• Experience with FPGA prototyping, hardware emulation, or post-silicon validation.
• Familiarity with low-power design techniques, including clock gating, power domains, and power optimization.
• Experience with advanced semiconductor process technologies, including 7nm, 5nm, 3nm, or below.
• Experience with ASIC designs that have successfully completed tape-out and silicon bring-up.

• Deliver high-quality microarchitecture specifications and production-ready RTL for AI accelerator and SoC functional blocks.
• Meet functional, performance, power, and area requirements.
• Successfully integrate designed blocks into larger ASIC/SoC subsystems.
• Identify and resolve complex RTL, timing, and functional issues.
• Collaborate effectively with architecture, verification, and physical design teams.
• Contribute to successful ASIC tape-out and silicon validation.

Why Join Xscend?

At Xscend, you will have the opportunity to work on next-generation AI computing and semiconductor technologies. You will contribute directly to advanced AI accelerator and high-performance SoC designs, collaborate with experienced ASIC engineers, and solve challenging digital design and implementation problems.

We value engineering excellence, hands-on technical expertise, creativity, and the ability to transform advanced concepts into production-ready silicon.

Pay: $140,000.00 - $200,000.00 per year, * 401(k)

• Dental insurance
• Flexible schedule