Verification Engineers - ASIC & Networking

We are looking for multiple Senior Verification Engineers - ASIC & Networking for contracts through the end of June. High possibility of extending or converting to an FTE., · Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off

· Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios

· Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing

· Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions

· Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results

· Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels

· Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics

· Review testbench architecture and debug methodology; mentor junior engineers in verification methodology

· Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or 7+ years equivalent experience

· Minimum 5 years of professional experience in ASIC or SoC functional verification

· Hands-on expertise in SystemVerilog, UVM, or formal testbench development and maintenance

· Experience with metric-driven verification for planning, assertions, and functional coverage closure

· Experience verifying complex digital control and datapath logic, including RTL and system-level debug

Preferred Qualifications

· Background in space-based communications, wireless communications, modem, baseband, or DSP hardware

· Experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis

· Formal verification experience on production silicon (connectivity, register maps, arbitration, CDC, or security properties)

· Experience with interconnect or NoC verification covering performance, bandwidth, QoS, and deadlock analysis

· Experience verifying fault tolerance and reliability features (ECC, redundancy schemes, or fault injection)

· Experience developing C-based or portable stimulus for SoC, CPU boot, and firmware-driven test scenarios

· Experience applying AI, ML, or LLM tooling to stimulus generation, regression triage, or coverage analysis

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