Distinguished Engineer (DE) or Senior Director, Central Engineering - SoC Design & Modeling Methodol

This position will serve as the leader of workload and performance analysis, hardware/software (HW/SW) optimization and co-design (including AI workloads), and SoC architecture. Expertise in architecture, design, validation, HW/SW optimization, and co-design is required. Experience in platform design and translating customer-facing requirements into system-level requirements is highly desirable.

The role encompasses workload characterization, solution integration, performance and power tradeoffs, the development of advanced SoC architecture, modeling methodologies, and design enablement strategies across multiple product lines.

The ideal candidate is a recognized technical leader with deep expertise in workload and performance analysis, AI workloads, HW/SW co-design, and SoC architecture. You will partner with product groups, platform teams, and executive leadership to define and analyze products and SoCs for performance and workload analysis, and help co-optimize using next-generation design methodologies that accelerate innovation and enable reuse across the organization., Technical Leadership

• Define and drive the strategic roadmap for workload analysis and performance for both IPs and products across the company.
• Lead architecture performance reviews and technical direction for complex IP/SoC and subsystem developments.
• Establish best practices for hardware/software co-design and model-based development.
• Provide technical leadership for cross-functional teams spanning architecture, design, verification, emulation, and software.

AI-Driven Engineering Innovation

• Define and analyze AI workloads and the performance required for these workloads.

Organizational Leadership

• Build and lead high-performing engineering teams.
• Mentor directors, principal engineers, and distinguished engineers.
• Foster collaboration across Central Engineering, Product Groups, and external partners.
• Influence long-term semiconductor technology and platform strategy.

• MS or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (Ph.D. highly desired)., * 15+ years of experience in semiconductor or SoC development.
• 8+ years of technical leadership experience.
• Proven experience leading performance and workload analysis and HW/SW co-optimization.

Technical Skills

• Strong understanding of:
• Performance analysis
• Workload analysis
• AI workloads
• SoC architecture and integration
• Digital design methodologies
• IP and subsystem development
• Hardware/software co-design
• SoC verification methodologies
• Hands-on experience with:
• Performance and workload benchmarking
• Virtual platforms and executable specifications
• SoC performance modeling
• Design and verification automation flows

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.