Sr. Principal Digital Design Engineer

Insight Global is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following:

• Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data compression, AI/HW accelerators) * Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL * Work with cross-functional project teams (DV, PD, System/Firmware) to define product specifications (PPA), system architecture, HW/SW partitioning, and execution plan * Lead improvements to design methodology to maximize efficiency and predictability * RTL implementation in SystemVerilog of communication/DSP/packet-processing functions * Block-level verification including creation of Verilog or UVM testbenches * System-level verification in UVM+SysC environments including test case creation/debug, functional coverage specification, and code coverage analysis * Perform preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis * Perform design quality checks including lint, CDC and DFT-readiness checks * Support emulator-based verification including debug of SW driven test cases * Post silicon bring-up support and debug in lab; support system integration and production testing Provide technical leadership in the ASIC design team to develop and productize next generation communication and data center SoCs

• Expert in digital design including micro-architecture definition and area/power/timing optimization * Solid understanding of high-speed interfaces (Ethernet/PCIe), particularly MAC/PCS (or Transaction/Data Link/PHY logical) layers, and associated clocking, reset, and CDC considerations * Experience with performance modeling and analysis, including performance constraint identification and optimization * Extensive experience with ASIC front-end design flow including RTL coding (SystemVerilog), directed/randomized verification, simulation/emulation debug, lint/CDC checks, synthesis, power analysis and timing closure support * Knowledge of communications/DSP/FEC algorithms and experience with power/area efficient fixed-point ASIC implementation a plus * Familiar with SoC integration, including clock/reset architecture, bus protocols, embedded CPUs * Strong logical and creative problem-solving skills with excellent analytical and debugging skills * Solid written and verbal communication skills * Flexibility to ramp quickly on new technologies, products, and methodologies * Self-motivated with ability to provide leadership and work effectively in fast-paced environment BS in Electrical Engineering or related + 11 years of experience, or MS + 9 years of experience, or Ph.D. + 6 years of experience