Vice President, Platform Solutions Architect

• Set architectural direction for the AI compute engine and its integration with the broader SoC,

in partnership with the team’s AI and system architecture leads

Interconnect, Memory & I/O Architecture

• Direct on-chip interconnect and coherency fabric architecture (NoC topology, protocol) to meet

bandwidth and latency requirements across compute, memory, and I/O

• Own memory subsystem architecture - on-die SRAM, external memory, and expansion

interfaces - sized and tiered to the demands of large-model inference workloads

• Guide I/O architecture and offload engine design, ensuring the platform integrates cleanly into

customer server and rack architectures

Verification, Signoff & Physical Integrity

• Own signoff across the entire SoC: functional verification strategy and coverage closure,

physical verification (DRC/LVS, timing), and signal and power integrity

• Build the verification and signoff cadence - design reviews, formal methods, coverage gates

• that catches issues early rather than at final tape-out

• Own power architecture and intent (UPF) across the chip, balancing performance targets

against thermal and power delivery constraintsCustomer Solutions & Product Engineering

• Translate SoC architecture into end solutions for customers: reference designs, system-level

integration guidance, and technical engagement through early customer programs

• Partner with the Product Engineering team on manufacturability, yield, and chip-level security

considerations from architecture definition through production

• Represent the architecture team in customer-facing technical discussions, ensuring platform

System Architecture, System-on-a-Chip (SoC), Artificial Intelligence (AI), Performance Modeling, Architectural Services, Memory Hardware, Input/Output, Topology, Server Architecture, Functional Testing, * 15+ years in semiconductor architecture or SoC design, with at least 5 years in senior

technical leadership owning full-chip architecture

• Demonstrated ownership of SoC architecture end-to-end: system definition, cross-block PPA

tradeoffs, and signoff through tape-out

• Experience building and leading multidisciplinary architecture teams spanning system

architecture, interconnect, memory, verification, and physical design

• Track record of translating chip architecture into deployable solutions for external customers,

not just internal specs

Strongly Preferred

• Architecture experience with AI/ML accelerators, inference-optimized SoCs, or datacenter-

class compute silicon

• Experience with memory subsystem architecture for large-model or high-bandwidth workloads

(tiered memory, coherency, capacity/bandwidth scaling)

• Experience serving hyperscale cloud or datacenter infrastructure customers, and

understanding of their technical evaluation and adoption process

• Familiarity with RISC-V or other open ISAs, and with confidential computing / secure

execution as it relates to silicon architecture

• Experience managing the interface to external back-end design and foundry partners,

including netlist quality, DFT, and signoff handoff

Leadership Qualities

• Operates as the final technical authority across the SoC: comfortable making binding

architecture decisions and defending them under scrutiny

• Can lead senior, specialized architects (system, interconnect, memory, verification) without

being the bottleneck - empowers depth while holding a coherent architectural vision

• Strong communicator across technical and business audiences; able to represent the platform

directly to hyperscale customer engineering teams

• High tolerance for greenfield ambiguity and startup pace; builds structure and process where

none currently exists, without slowing the team down