Senior Applications Engineer

Duties: Drive and grow formal verification business across business accounts. Work with the ATM (Account Technology Manager) and AMS (Account Managers) to drive the adoption of formal products and apps in customer’s verification flow. Work closely with account teams to uncover and qualify formal verification engagement opportunities including constructing and driving top-down and bottom-up plans. Develop strategy for driving formal business. Provide formal verification and hands-on experience. The role involves designing and executing a customer adoption and deployment process for Siemens Questa formal verification solutions within semiconductor and system organizations. Working with Account Managers (AMs) and Account Technology Managers (ATMs), this role evaluates customer verification challenges, develops technical engagement plans, conducts product evaluations, and implements formal verification methodologies into customers’ existing design and verification flows. The process includes opportunity assessment, customer presentations and demonstrations, technical deployment, training, adoption tracking, and strategic account planning. The equipment used includes Linux- and Windows-based computer workstations and laptops, secure remote access tools, video conferencing platforms, and issue-tracking systems such as Confluence JIRA. The system consists of the Siemens Questa formal verification software suite integrated into customer environments, including RTL design flows, Makefile-based build systems, Python scripting frameworks, and regression testing infrastructures operating on-premise or cloud computing resources. The role does not design end-user semiconductor products directly; rather, enables deployment of formal verification solutions and workflows that enable customers to verify complex digital designs such as microprocessors, CPUs, GPUs, system-on-chip (SoC) devices, and other integrated circuits, which improves verification coverage, identifies design defects earlier, and accelerates customer product development cycles.

Requirements: Employer will accept a Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 60 months of experience in the job offered or in a Applications Engineer-related occupation. Alternatively, Employer will accept a Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 36 months of experience in the job offered or in a Applications Engineer-related occupation.

Position requires experience in the following:

1. Utilizing RTL design concepts including clocking, resets, state machines, FIFOs, datapaths, and arbiters.

2. Writing and debugging SystemVerilog assertions, assumptions and cover properties

3. Working with Formal Verification software such as Synopsys VC Formal or Cadence JasperGold

4. Working with formal techniques including debugging counter-examples and creating cut-points.