Senior DFT Design Engineer

The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge technologies including FPGA, processor, DSP, SERDES, IO, 2.5D/3D multi-die packaging, and other advanced solutions that will drive future innovation. As a Senior DFT Design Engineer, you will be responsible for DFT architecture and implementation, including DFT specifications, test logic insertion, test mode timing constraints, ATPG, and pre-silicon validation. You will also contribute to the development of DFT methodologies and flows to improve pre-silicon and post-silicon validation processes. This role provides the opportunity to work closely with IP and integration design teams to understand design and functional behaviors of complex circuits, as well as with test development teams to meet manufacturing test requirements for coverage, cost, yield, and silicon bring-up/debug., * Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.

• Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.
• Collaborate with IP and integration design teams to align DFT features with design functionality and timing.
• Partner with test development teams to support silicon bring-up, debug, and production readiness.
• Contribute to DFT methodology and automation flows to enhance scalability and efficiency.
• Ensure manufacturability goals are met, including test coverage, test cost optimization, yield improvement, and debug support.

• Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience in the following - OR - Master’s degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of industry experience in the following:
• 8+ years of experience in DFT design and verification at both RTL and gate level.
• Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools Design automation experience and proficiency in scripting languages such as Perl/TCL.
• Preferred Qualifications: Experience with test compression, BIST (MBIST/LBIST), and advanced fault models.
• Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.

Job Type

Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations

Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $187,000 - $270,700 USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.