Front End Design Engineer

APPLE INC has the following available in Austin, Texas. Convert RTL designs into netlists using industry-standard RTL synthesis tools. Optimize power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies. Understand RTL code written in Verilog and SystemVerilog languages, correlate it to gate-level circuits, and guide the development of optimal RTL solutions. Perform Clock and Reset Domain Crossing (CDC,RDC) checks to ensure the design’s robustness against metastability-related problems and lint checks. Perform logical equivalence checks to ensure correctness of the generated netlist and support ECO generation activities. Perform static timing analysis (STA) to identify critical paths in the design, then propose solutions spanning both physical implementation and microarchitectural optimizations. Analyze RTL simulation waveforms using industry standard simulator tools to understand the design’s intent and common signal activity pattern. Lint checks to ensure the overall quality of RTL code. Collaborate effectively with internal R&D teams. 40 hours/week.

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field and 1 year of experience in the job offered or related occupation.

Experience and/or education must include:

Synthesizing RTL designs using Design Compiler/Genus into netlist

Understanding RTL and make RTL updates for PPA

Creating unit testbench to verify RTL updates

Working with simulation waveform to understand design intent

Performing Static Timing Analysis (STA) and achieving timing closure

Performing Lint checks to ensure RTL quality

Performing Clock Domain Crossing checks (CDC)

Performing Reset Domain Crossing Checks (RDC)

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