Dsp Engineer

We are seeking an experienced DSP Engineer to define communication system architectures and develop advanced digital signal processing algorithms for high-performance ASIC-based products. In this role, you will work at the system architecture level, create detailed system models, and drive the design from concept through implementation and verification. You will focus on digital communication systems, physical layer (PHY) development, and communication algorithm design, rather than FPGA development, embedded software, or robotics engineering. This position is ideal for someone who has personally developed communication algorithms and system architectures and enjoys collaborating closely with ASIC design and verification teams., * Define end-to-end communication system architectures for high-performance ASIC-based products.

• Design and develop DSP algorithms for digital communication systems and physical layer (PHY) implementations.
• Design and develop physical layer (PHY) communication systems and signal processing solutions for wireline and high-speed data communication applications.
• Create bit-accurate and fixed-point system models using C and MATLAB to accurately represent communication algorithms and architectures.
• Develop simulation environments to evaluate system performance, explore architectural trade-offs, and validate design decisions.
• Generate verification vectors to support ASIC design and verification teams and ensure accurate implementation of system models in hardware.
• Collaborate closely with ASIC implementation teams to translate system and algorithm models into RTL and final ASIC designs.
• Support system-level verification by correlating modeled performance against RTL and ASIC implementations and driving closure on discrepancies.
• Define architecture specifications, system requirements, verification strategies, and detailed test plans for communication subsystems.
• Develop golden models for key DSP and communication algorithms to serve as reference implementations for verification.
• Perform performance modeling and analysis of communication systems, including evaluation of equalization, timing recovery, channel estimation, and synchronization algorithms.
• Support lab bring-up and hands-on validation of ASIC-based communication systems, including comparison of measured and modeled performance.
• Work with cross-functional ASIC, verification, and hardware teams throughout the development lifecycle to ensure robust, high-performance system delivery.
• Contribute technical expertise in Ethernet, twisted-pair, and other wireline communication architectures to guide system design.
• Ensure that DSP and communication algorithms are optimized for ASIC implementation, including fixed-point representation and hardware efficiency considerations.

• Bachelors degree with 8+ years, Masters degree with 6+ years, or PhD with 3+ years of relevant industry experience in a related field.
• Strong preference for candidates with a Masters or PhD in Electrical Engineering or a closely related discipline.
• Deep expertise in digital communication systems, including high-speed and wireline communication architectures.
• Deep expertise in digital signal processing (DSP) theory and practical implementation.
• Strong experience in physical layer (PHY) architecture and PHY layer development.
• Proven experience in communication algorithm development, including designing and developing new algorithms rather than only implementing existing designs.
• Strong programming experience in C, with preference for C over C++.
• Experience using MATLAB to develop communication system models and perform algorithm development and analysis.
• Experience defining communication system architecture and developing DSP algorithms for ASIC-based products.
• Experience creating bit-accurate and fixed-point models for communication and DSP algorithms.
• Experience developing simulation environments to evaluate system performance and validate architectural decisions.
• Experience generating verification vectors and collaborating with ASIC implementation teams.
• Experience supporting ASIC implementation efforts and working closely with ASIC design and verification teams.
• Familiarity with ASIC architecture and development flows, including RTL correlation and validation.
• Hands-on lab validation experience for communication systems or ASIC-based products.
• Expertise in DSP algorithms such as equalization, timing recovery, channel estimation, synchronization, signal detection, and performance modeling.
• Experience with fixed-point modeling, golden model development, verification vector generation, and ASIC implementation support.
• Experience with Ethernet, twisted-pair communication systems, wireline communication architectures, high-speed data communications, and PHY layer development.

This is a Permanent position based out of Irvine, CA. Pay and Benefits

The pay range for this position is $100000.00 - $200000.00/yr.

Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.

ESPP – purchase shares at a 15% discount on the market price, up to $25k limit 401k – company manthes at 100% of the first 6% of salary As far as RSUs, I have recently seen Principal candidates receive one-time grants of approximately 4000 shares, vesting quarterly over 4 years. The grant is given not long after hiring (the timing varies depending on the precise hire date), and the first shares vest one quarter after the grant date. There is an opportunity for annual refresh grants. Job Type & Location

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