Senior C++ Design Verification Engineer

We are looking for experienced Senior Design Verification Engineers with strong C++ programming skills and hands-on experience in hardware/system-level design verification. The ideal candidate should have experience with C++-based verification methodologies, preferably in DSP and/or Ethernet protocols. Required Skills & Qualifications

• 8+ years of experience in Design Verification, System Verification, or related engineering roles.
• Strong hands-on experience with C++ programming.
• Experience using C++ for design verification.
• Knowledge of System-level verification methodologies.
• Experience with Teal or Trust-based verification environments.
• Strong understanding of DSP (Digital Signal Processing) and/or Ethernet protocols.
• Experience in networking, communication systems, or hardware verification is preferred.
• Ability to develop, execute, and debug verification test cases.
• Strong debugging, problem-solving, and analytical skills.

Preferred Skills

• Experience with DSP verification.
• Experience with Ethernet protocol verification.
• Networking and communication hardware experience.
• Experience in C++-based verification frameworks.

Important Notes

• C++ is mandatory for verification.
• Verification experience using Teal/Trust is preferred.
• Candidates with only SystemVerilog (SV) or UVM verification experience are not suitable.
• Candidates must have 8+ years of experience.
• Candidates must be willing to work onsite in Massachusetts, USA.