Lead Software Engineer

Software Engineering, Product Engineering, Software Engineering, Universal Asynchronous Receiver-Transmitter (UART), Boundary Scan, PCI Express (PCI-E), IXIA, RTL Design, SystemVerilog, Digital Circuit Design, Application or Product Engineering background with minimum 5 to 20 years of experience is required in HW Assisted Verification. Knowledge of FW/SW/Driver with Linux Boot bring up experience is an essential requirement. Knowledge of PCIe, HBM and JTAG/UART protocols is must.. ENET protocol & testers like Virtual IXIA is plus.

Skills Requirements

Digital design with systeme verilog RTL coding from Synthesis point of view..

Experience with emulator ZeBu, Palladium & Veloce.

FPGA Protyping experience with HAPS, Protium & ProFPGA is plus.

Ability to put together emulation top level wrapper with DUT/System Level, clocks/reset & FPGA partitioning/Place & Route timing closure for successful model build.

Knowledge of Python, C/Perl scripting is a must.

Expertise in HW assisted Verification TestBench environment : UVM, C++/System C is desired.

Experience integrating and bringing up PCIe Gen6 Protocol Transactor Integration with QeMu is required.

Kernel boot, Linux Boot sequences knowledge & debug is must.