Block Verification Technical Lead

Each position involves leading 3 to 4 verification engineers, developing SystemVerilog/UVM environments, driving coverage closure and collaborating closely with RTL design teams., The main challenge is ensuring correct interrupt handling, synchronization and system initialization. Position 2: System Router & Interconnect Verification

Focuses on verification of the system router and communication fabric connecting processor cores, memory and other SoC components.

The main challenge is ensuring correct transaction routing, ordering, traffic handling and deadlock prevention under heavy workloads., * Own block verification plans, execution and tapeout signoff.

• Develop and maintain SystemVerilog/UVM testbenches, reference models, scoreboards and assertions.
• Drive functional coverage, regressions, debugging and bug closure.
• Lead and mentor 3 to 4 verification engineers.
• Review verification environments, distribute tasks and resolve technical challenges.
• Collaborate with RTL designers on microarchitecture and interface verification.
• Develop reusable verification components for SoC integration.
• Improve regression automation, CI and verification workflows.
• Report verification progress, risks and signoff readiness.

• 6+ years in ASIC/SoC design verification, including at least one block taken to tapeout.
• Expert SystemVerilog and UVM, including testbench architecture from scratch.
• Strong functional coverage, SVA and verification signoff experience.
• Proven technical leadership, verification planning and mentoring.
• Deep knowledge of at least one of: CPU cores, cache controllers or coherent interconnects.
• Working knowledge of AXI and CHI protocols.
• Experience with VCS, Questa or Xcelium and debugging tools.
• Python/Bash scripting and regression automation.
• Relevant engineering degree or equivalent experience.
• Fluent English.

Important: Direct ASIC/SoC functional verification experience, including UVM architecture, coverage closure, tapeout signoff and technical leadership, is essential. RTL design, FPGA development or verification execution alone is insufficient. Optional / Desired

• RISC-V, CPU cluster or AI accelerator verification.
• Cache coherence protocols, including CHI, ACE and MESI/MOESI.
• Memory ordering verification.
• GitLab CI and verification automation.
• Previous people management experience.
• System Control position: Interrupt controller, synchronization or boot verification experience.
• System Router position: NoC, coherent interconnect, transaction ordering or traffic verification experience.

• Flexible working hours
• Hybrid model, 4 days office, 1 day from home
• 1 week per year working from anywhere
• 25 days annual leave plus December 24 and 31
• Monthly food allowance
• Private medical insurance
• Relocation bonus
• Housing search support
• Visa support, subject to approval
• Family relocation support, subject to eligibility
• Virtual shares, subject to plan terms
• Language classes
• Tax incentive