CPU Micro-architect

We are seeking a talented CPU Micro-architect to join our team, where you will play a pivotal part in shaping next-generation processors for AI, high-performance computing, and edge devices. In this role, you will be responsible for exploring new features and optimizing the microarchitecture of high performance OoO CPU cores. You’ll collaborate with cross-functional teams and external partners to push the boundaries of processor design.

• Improve the benchmarks and real-use-case performance (IPC, power/area efficiency) of a state of the art (SOTA) OoO CPU core, covering all aspects of the micro-architecture, including core pipelines, branch prediction, prefetching, and cache/TLB hierarchy.
• Work with the performance simulation team to model the microarchitecture of the SOTA core.
• Correlate simulation results against silicon measurement data, and perform thorough root cause analysis and debugging to identify, diagnose, and rectify any discrepancies, ensuring model accuracy and reliability.
• Explore new features and ISA extensions (e.g., vector extensions, memory safety features, security enhancements, etc.) to drive performance enhancements, optimizing efficiency, reliability, and protection.
• Identify and resolve performance bottlenecks through modeling and prototyping.
• Develop performance models (as needed) and micro testbenches to improve and validate key performance features in the CPUs.
• Collaborate with cross-functional teams and external partners to ensure seamless integration of designs.

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a Ph.D.
• Extensive background in CPU microarchitecture design, with a strong understanding of computer architecture principles, including pipelining, superscalar design, cache hierarchies, coherency, and multi-core systems.
• Strong experience in performance analysis, modeling, and optimization, as well as common mobile benchmarks like GB6 and SpecInt17, and real use cases such as games and web browsing.
• Familiarity with Arm ISA (Armv8/v9) and extensions, or equivalent ISAs (x86 and RISC-V), and their impact on microarchitecture.
• Proficiency in reading - and writing as needed - hardware description languages (Verilog/SV) and programming languages (C++, Python) for modeling and simulation.
• Ability to correlate simulation performance results against hardware performance metrics (cache misses, TLB misses, pipeline stalls) to ensure optimal performance.
• Excellent problem-solving skills and the ability to work in a collaborative, interdisciplinary environment., This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

At Samsung - SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,000 and $251,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us!, The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance- and power-optimized IP solutions that support advanced system modeling and real-world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments.

Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next-generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth.