Toolchain/Digital Design Engineer

Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or Rust). - Map quantified requirements into physical standard-cell routing and logic structures. - Run synthesis, place-and-route, and area/power/timing (PPA) estimates to sweep architectural scaling limits (max model parameter count, max whitelist/blacklist size). - Interface with the Principal Investigator and Hardware SME to ensure correct RTL generation and physical implementation. Required Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog/SystemVerilog/VHDL), and digital logic synthesis. - Strong Scripting and automation skills for EDA flows. - US Person (Citizen or Permanent Resident) eligible to work on defense-related technology.