Senior IP Design Engineer
Role details
Job location
Tech stack
Job description
As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA / Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows.
Requirements
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Strong SystemVerilog RTL design experience
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FPGA/Adaptive SoC design flow: synthesis, P&R, timing closure
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High-speed digital interfaces: 100GbE / PCIe Gen5 / AXI
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Vivado / Vitis toolchain expertise
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Python/Tcl, Git, CI/CD experience, If you are a Senior IP Design Engineer with strong FPGA RTL, high-speed interface IP and Xilinx toolchain experience, please apply with your CV for immediate consideration
