Field-Programmable Gate Arrays Engineer

Anson McCade
Stevenage, United Kingdom
13 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Intermediate
Compensation
£ 75K

Job location

Stevenage, United Kingdom

Tech stack

Computer Engineering
Digital Electronics
Field-Programmable Gate Array (FPGA)
Static Timing Analysis
SystemVerilog
Verilog
VHDL
Scripting (Bash/Python/Go/Ruby)
Hardware Testing
Low Latency

Job description

This opportunity stands out for its potential to combine technical leadership with hands-on FPGA expertise, contributing to complex high-performance, low-latency, or high-throughput systems. You will lead, mentor, and grow a talented team while overseeing FPGA architecture, design, and implementation across multiple projects.

Requirements

  • British Citizen or a Dual UK national with British citizenship
  • BS/MS/PhD in Electronic Engineering, Computer Engineering, or a related field
  • 10+ years of FPGA or digital hardware design experience, including 3-5 years in a leadership/management role
  • Strong experience with RTL design (VHDL/Verilog/SystemVerilog), simulation, synthesis, timing analysis, and hardware validation
  • Knowledge of high-speed interfaces, DSP, control logic, and Image Processing
  • Understanding of hardware-software co-design, embedded systems, and verification methodologies
  • Experience leading cross-functional teams and delivering complex FPGA systems from concept to production
  • Excellent interpersonal, communication, and leadership skills
  • Exposure to aerospace/defence, high-performance computing, or telecommunications domains
  • Familiarity with FPGA toolchains, scripting, and automation

Benefits & conditions

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  • Base salary: Up to £75,000 Per Annum
  • Company Bonus: Up to 21% of base salary
  • Pension: Up to 14% total contribution (employer + employee)
  • Flexible working: Compressed hours and hybrid arrangements available
  • Enhanced parental leave: Up to 26 weeks maternity/adoption/shared parental leave; enhancements for paternity, neonatal, and fertility support
  • Facilities: Subsidised meals, free car parking, and excellent on-site amenities

About the company

A leading integrated defence company seeks an experienced FPGA Engineering Manager to lead a high-performing team developing cutting-edge FPGA-based solutions. This role offers the opportunity to shape future capabilities, drive technical excellence, and mentor a team of engineers in a fast-growing Electronic Engineering Function.

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