Junior Digital IC Design Engineer

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Graz, Austria
1 month ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English, German
Experience level
Junior
Compensation
€ 38K

Job location

Graz, Austria

Tech stack

C++
Computer Programming
Software Debugging
Logic Synthesis of Circuits
Python
Matlab
Micro Electro-Mechanical Systems (MEMS)
Static Timing Analysis
Verilog
VHDL
Application Specific Integrated Circuits

Job description

We are looking for a Digital IC Design and Verification Engineer. In this role you will play an integral role in defining and developing chips that support our product, technology and loudspeaker roadmaps.

This position offers the opportunity to work closely with a multidisciplinary team of dedicated ASIC, hardware, and software engineers in a dynamic environment.

Technical Expertise Personal Evolution Autonomy Responsibilities

  • Digital design and verification of integrated circuits for MEMS driver ASICs.
  • System-level modelling and analysis of MEMS driver AISCs.
  • Interpretation of block specifications and contribution to the definition of digital architectures.
  • Implementation of digital verification using advanced verification methodologies (MDV).
  • Support of effort and area estimation for digital modules.
  • Execution of synthesis and static timing analysis (STA).
  • Contribution to and implementation of DFT strategies.
  • Hands-on laboratory evaluation of products.

Future Responsibilities

  • Support and further develop design and verification methodologies for optimal chip performance.
  • Lab and production test specification, lab verification, failure analysis, and debugging at both chip and block levels
  • Support the implementation of production tests and ramp-up activities

Requirements

  • Master's degree in Electrical/Electronic Engineering.
  • 2 - 5 years of relevant industry experience.
  • Solid understanding of digital ASIC design, including RTL coding in Verilog or VHDL.
  • Experience with modelling of mixed-signal systems, preferably using MATLAB.
  • Good understanding of advanced verification methodologies.
  • Knowledge of the Cadence digital design environment is a plus.
  • Programming skills in Python, C++, or similar are a plus.
  • Self-motivated and able to work independently with minimal guidance.
  • Strong teamwork skills.
  • Fluent in English or German.

Benefits & conditions

  • Range of the annual gross salary from € 47,000 depending on experience, qualifications, etc.; legal minimum annual gross salary on a full-time basis: € 38,184.
  • Additional incentives including bonuses and profit-sharing opportunities.

Benefits: We offer a range of perks including lunch subsidies, language courses, well-being and summer childcare subsidies, future provision, and many more. At our location you will find free parking slots, a canteen and a snack buffet.

Lunch Dispent

Work Live Friendly

Free Refreshments

Bonus

Home Office

Development

Jobrad Public Transportation

About the company

USound is disrupting the audio industry, setting new standards in audio experience, and maximizing the degrees of freedom for wearables and hearables. We are leaders in acoustic solutions based on MEMS speakers by enabling our customers to bring new revolutionary audio products to the market. USound achieves this through radical miniaturization, power reduction, and increased production efficiency.

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