Senior Digital Design Engineer

Job Title: Senior Digital Design Engineer

Location: Netherlands

Job Type: Permanent

Salary: DOE

Role Overview:

Our client is a market-leading semiconductor company developing high-performance precision timing solutions built on a unique combination of advanced MEMS and CMOS technologies.

Key Responsibilities:

-Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD). -Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL. -Developing standalone test benches to verify the RTL behaviour. -Writing and verifying SystemVerilog Assertions (SVA) for a design. -Writing timing constraints and clock definition for synthesis and place and route tools. -Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise. -Understanding various design tradeoffs including timing/area/power and knowing how to improve them. -Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time). -Cross-functional interactions and communication with various teams including analog, verification, backend, system, and test engineering teams. -Post-silicon bring-up, validation, and debugging.

Experience Required:

-Masters degree in electrical engineering -5+ years of industry, work experience -Proficient in Verilog and SystemVerilog. -Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc. -Experience in designing mixed-signal digital logic. -Basic understanding of Discrete Time Signal Processing theory, FIR, and IIR filter design. -Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA. -Skilled in scripting languages Perl/Tcl/Python. -Excellent verbal and written communication skills in English.

Desired Characteristics & Attributes:

-Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience. -2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing. -2-5 years of experience in designing Digital Phase-Locked Loops (DPLL). -Experience in complex FSM design. -Familiarity with MATLAB, Simulink, or any other high-level modelling tools. -Experience in low-power digital design flow. -Basic understanding of Control Theory.

If you would like to

Masters degree in electrical engineering -5+ years of industry, work experience -Proficient in Verilog and SystemVerilog. -Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc. -Experience in designing mixed-signal digital logic. -Basic understanding of Discrete Time Signal Processing theory, FIR, and IIR filter design. -Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA. -Skilled in scripting languages Perl/Tcl/Python. -Excellent verbal and written communication skills in English., Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience. -2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing. -2-5 years of experience in designing Digital Phase-Locked Loops (DPLL). -Experience in complex FSM design. -Familiarity with MATLAB, Simulink, or any other high-level modelling tools. -Experience in low-power digital design flow. -Basic understanding of Control Theory.