Sr. RTL Design Engineer (Silicon Engineering)
Role details
Job location
Tech stack
Job description
- Evaluate architectural trade-offs based on features, performance requirements and system limitations
- Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
- Work closely with verification team to ensure all aspects of the design are covered and verified
- Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
- Participate in silicon bring-up and validation
Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 5+ years of experience in RTL implementation
PREFERRED SKILLS AND EXPERIENCE:
- Ability to solve complex problems including clock domain crossings and power optimization
- ASIC/SoC system integration experience
- Experience with multicore CPU subsystem design
- Experience with standard bus protocols (e.g. AXI, AHB, etc.)
- Experience with embedded processors
- Experience with high speed and low power design techniques
- Scripting skills (Python, TCL etc.)
- Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
- Ability to work in a dynamic environment with changing needs and requirements
- Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
- Enjoys being challenged and learning new skills
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical milestones, * To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. * 1157, or (iv) Asylee under 8 U.S.C. * 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
Benefits & conditions
$170,000.00 - $235,000.00/per year life insurance, parental leave, paid holidays, sick time, 401(k), retirement plan, stock options United States, California, Sunnyvale 390 West Java Drive (Show on map) Mar 12, 2026, ASIC Design Engineer/Senior: $170,000.00 - $235,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
