FPGA Engineer
Role details
Job location
Tech stack
Job description
Architecture & Development (VHDL Focused) Own FPGA RTL design using VHDL as the primary HDL. Develop reusable IP blocks including state machines, controllers, DSP modules, and memory interfaces.
Implement deterministic, low latency data paths for diagnostic imaging and acquisition systems.
Translate system requirements into FPGA architecture with complete traceability.
High-Speed I/O & Data Acquisition (MedTech) Implement and validate interfaces for precision ADC/DAC front ends: JESD204B/C, LVDS, MIPI, SPI, I C, UART.
Build high throughput acquisition and buffering pipelines using DDR4/DDR5 and AXI.
Ensure deterministic timing, synchronization, and clocking across modalities (Ultrasound/ CT/MRI/sensing subsystems).
Verification, Timing Closure & Toolflow Develop self checking VHDL testbenches for block and system level verification.
Use ModelSim/QuestaSim, Vivado Simulator, or Riviera PRO for simulation. Perform synthesis, P&R, timing analysis, and closure using Xilinx Vivado (preferred) or Intel Quartus.
Execute linting, CDC/RDC checks, and optimize power and resource utilization.
Debug via ILA/SignalTap, oscilloscopes, logic and protocol analyzers. Compliance, Documentation & Quality Support design controls and documentation for FDA, EU MDR, and global regulatory needs.
Contribute to requirements traceability (Jama/DOORS), risk management (ISO 14971), and verification per IEC 62304 for programmable logic.
Address safety (IEC 60601 1), EMC (IEC 60601 1 2), cybersecurity, FMEA, hazard analysis, and IP/SOUP assessments.
Requirements
Bachelor s or Master s in Electronics, Electrical, Computer Engineering, or related field.
Skills: -
Mandatory skills
- 4 10 years hands-on FPGA design experience with VHDL as the primary HDL.
- Strong experience with: Synchronous digital design fundamentals Clocking, CDC, reset-domain considerations Timing analysis and closure FPGA development using Xilinx/AMD or Intel platforms.
- Proven ability to develop complex state machines, DSP blocks, and interface logic in VHDL.
- Familiarity with lab bring-up and FPGA system debugging.
Benefits & conditions
We focus on building highly motivated engineering teams and thought leaders with an entrepreneurial mindset, centered on our core values of Passion, Respect, Openness, Unity, and Depth (PROUD) of knowledge. Our success lies in creating a fun, transparent, non-hierarchical, diverse work culture that focuses on continuous learning and work-life balance.
Rated by our employees as the Great Place to Work for according to the Great Place to Work survey. We offer you a comprehensive set of benefits to ensure that you have a long and rewarding career with us.
Our EVP
Be You Be Awesome is our EVP and it reflects our continuing efforts to create CitiusTech as a great place to work where our employees can thrive, both personally and professionally. It encompasses the unique benefits and opportunities we offer to support your growth, well-being, and success throughout your journey with us and beyond. Together with our clients, we are solving some of the greatest healthcare challenges and positively impacting human lives. Welcome to the world of Faster Growth, Higher Learning, and Stronger Impact.
