Networking Operating System Firmware Engineer

We are seeking a Networking Operating System Firmware Engineer to help bootstrap and scale the switching layer of our AI supercomputers. In this role, you will build and maintain custom NOS images from scratch, using open source components from SONiC, SAI, FRR, and related networking stacks while working across the Linux kernel, switch ASIC SAI/SDKs, platform drivers, control-plane services, and orchestration layers.

This is a software engineering role that requires a deep understanding of networking, NOS internals, switch hardware, and production systems. You will design, implement, test, and debug production NOS software across platform drivers, routing and control-plane state, ASIC programming, observability, and fleet integration. The engineer in this role should be able to work through ambiguous, open-ended technical problems and drive feature development across software, hardware, and vendor boundaries.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will

• Design, develop, and maintain custom NOS images for large-scale AI fabrics, using open source components from SONiC, FRR, and related networking stacks.
• Integrate, build and configure Linux kernel components, device drivers, switch ASIC SDKs, and SAI layers.
• Bring up new switch platforms, including thermal and fan control, power monitoring, transceiver management, watchdogs, OSFP CMIS, LEDs, CPLDs, and board-specific platform logic.
• Extend and customize NOS services for routing, telemetry, control-plane state, and distributed automation.
• Implement and debug route, neighbor, next-hop, and ECMP programming flows from control-plane intent through ASIC hardware state.
• Build software mechanisms that distinguish control-plane acceptance, SAI/SDK acceptance, and explicit hardware programming acknowledgement.
• Work with hardware teams to validate ASIC configurations, link bring-up, SerDes tuning, buffer profiles, and performance baselines.
• Evaluate switch silicon SDK releases, track vendor deliverables, and validate platform requirements with vendors and ASIC partners.
• Debug complex issues spanning kernel drivers, platform monitoring, NOS services, routing agents, orchestration services, hardware signals, ASIC state, and network topology.
• Integrate switches into fleet-wide monitoring, remote diagnostics, telemetry pipelines, and automated lifecycle workflows.
• Develop robust CI/build pipelines for reproducible NOS builds and controlled rollout across the fleet.
• Support factory bring-up and qualification all the way through mass deployment.
• Collaborate on networking protocols and technologies that improve performance and reliability at AI factory scale.

• Proven experience working with SONiC or comparable NOS stacks such as FBOSS, Cumulus Linux, Arista EOS, Junos PFE-level integration, or equivalent platform software.
• Strong software engineering fundamentals: clear interfaces, data models, state-machine design, error handling, testing, observability, performance debugging, and maintainable C/C++, Python, Go or Rust code.
• Experience with Linux kernel internals, network device drivers, platform drivers, hwmon, I2C/SMBus, CPLDs, or board-level platform software.
• Experience integrating or debugging Broadcom, Marvell, NVIDIA, Intel, or comparable switch ASIC SDKs and SAI implementations.
• Understanding of L2/L3 forwarding, ECMP, RoCE, BGP, QoS, PFC, buffer tuning, and telemetry.
• Experience with platform bring-up and board-level debugging across thermal, fan, power, transceiver, LED, watchdog, CPLD, or OSFP CMIS flows.
• Experience with OpenConfig gNMI interfaces, YANG data models, or structured telemetry is helpful.
• Familiarity with CI/CD pipelines, distributed config and state management, reproducible builds, and large-scale automation.
• Ability to independently drive ambiguous NOS or platform feature development from problem definition through implementation, validation, rollout, and debugging across software, hardware, and vendor boundaries.
• Familiarity with Rust or Go is a plus.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

$266K - $445K medical insurance, dental insurance, vision insurance, parental leave, paid time off, paid holidays, 401(k), retirement plan United States, California, San Francisco May 07, 2026 About the Team

OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. Role summary

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity., At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.