Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning

• Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist)
• Develop and maintain dashboards for power rollups
• Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation
• Give feedback to designers and architects on how to reduce power
• Make power measurements in the lab and correlate back to simulations.
• Work with Emulation engineers to model chip-level power consumption

A day in the life Depending on the state of the project, you may find yourself working on the following:

• Working with designers, architects and verification engineers to come up with worst-case vectors for power analysis or IR analysis
• Root cause causes of low annotation or low switching coverage with vectors
• Develop & maintain dashboards to track power consumption
• Run tools like Power Artist to identify power saving opportunities and feed these back to the design team.
• Work with emulation engineers to model chip level power consumption and correlate with simulation
• Do post-silicon power measurements and correlate with simulation.

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We're searching for an experienced SoC Power engineer with a background in Power analysis with a proven track record of handling challenges at scale. In this role, you'll be working directly with architects, designers, verification engineers, software teams, and Physical Design experts - defining best practices to reduce power and model power consumption with high accuracy., * Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering

• BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS
• Expert on power analysis tools like PrimePower, PowerArtist or similar
• Ability to give feedback to RTL designers and Physical Designers on how to reduce power
• Highly proficient with scripting language (Tcl, Perl, Python or similar)
• Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level
• Understanding of lab equipment use and capable of doing lab power analysis
• Knowledge of deep circuit-level chip power, * Familiarity with Make or similar for automation of power rollups
• Experience with RTL design (System verilog)
• Familiarity with EMIR analysis tools (Redhawk / Voltus)
• Experience with Zebu Emulator platform

3.53.5 out of 5 stars Cupertino, CA $159,200 - $247,600 a year - Full-time, Pulled from the full job description

• AD&D insurance
• Parental leave
• Health insurance
• 401(k) matching
• Paid time off
• Vision insurance
• Dental insurance, The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits. USA, CA, Cupertino - 183,000.00 - 247,600.00 USD annually USA, TX, Austin - 159,200.00 - 215,300.00 USD annually

AWS Utility Computing (UC) provides product innovations - from foundational services such as Amazon's Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS's services and features apart in the industry. As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power today's AI workloads in datacenters all around the world. As a Sr. SoC Power Engineer, you'll contribute to the project at the ground level by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption of our machine learning accelerators.