Graphics Post silicon Test & Methodology Engineer

Apple Inc.
Austin, United States of America
5 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Intermediate

Job location

Austin, United States of America

Tech stack

Apple Products
Software Debugging
Perl
Python
JMP (Statistical Software)

Job description

Do you love creating solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, large subsystems. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll craft and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices.

In this role, you will be a cross functional liaison responsible for Pre-silicon inputs and debug on post-silicon to enable implementation, validation, and improvement of power efficiency in our GPU designs., Are you a competent problem solver who thrives under pressure to find creative time critical solutions to chart the future of GPU designs at Apple? If so, we would love to hear from you.

You will isolate post-silicon issues into Test, Process, Design or interactions, drive stop gaps using PFA/EFA, and make corrective actions in future designs.

Ensure manufacturing deliverables for Power/LVcc Design targets and work on power optimization by collaborating with Product and Silicon Validation teams

You will compare and close Post-silicon to Design targets

Requirements

Experience in DFT - ATPG and BIST

Device physics experience

Perl or Python coding experience

BS + 3 years of relevant experience

Preferred Qualifications

Good understanding of STA concepts - explain a PT report

Good understanding of PVT (Process Voltage and Temperature) corners, and Guard bands

Expertise in data analyses using Statistical analyses tools (JMP) with a good understanding of statistics

Familiarity with failure analyses techniques like emissions, DLS, LVI/LVP is desired

Familiarity with IR/IVD analyses to help drive correlation between silicon and design is desired

ATE experience is a plus

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