ASIC Digital Design, Sr Manager

Synopsys
Sunnyvale, United States of America
2 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior
Compensation
$ 306K

Job location

Sunnyvale, United States of America

Tech stack

Artificial Intelligence
Software Debugging
Digital Architecture
Digital Arts
Logic Synthesis of Circuits
Electronic Design Automation
Perl
Python
PCI Express
Tcl (Programming Language)
Scripting (Bash/Python/Go/Ruby)
Application Specific Integrated Circuits

Job description

You are an experiencedASIC Digital Design Managerwithstrong handson expertise in USB digital design and architecture, capable ofleading a team while remaining deeply engaged in technical execution. You bring extensive experience defining and implementingRTL and microarchitecture for complex, highspeed interface IP, combined with proven teamlead and peoplemanagement skills.

You setting technical direction with your team, making architectural tradeoffs, and driving design decisions . You are comfortable working directly with RTL, reviewing detailed design implementations, and guiding engineers through complex debug and convergence challenges. Your background includes exposure to USB or similar protocols.

As a experienced leader, you foster a culture of accountability, collaboration, and technical excellence. You mentor engineers through handson guidance and design reviews, communicate clearly across disciplines, and work closely with crossfunctional teams to deliverhighquality, siliconproven USB IP.

What You'll Be Doing:

Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance, mentoring, and performance management.

  • OwningUSB digital architecture and RTL design execution, remaining handson while leading design efforts at block, subsystem, and IPintegration levels.
  • Defining microarchitecture, design specifications, and implementation approaches for highperformance, powerefficient, and scalable PCIe designs.
  • Leading endtoend digital design activities, including architecture definition, RTL development, debug, design convergence, and postsilicon support.
  • Planning and prioritizing design work, balancing handson technical involvement with team execution, schedules, and resource needs.
  • Driving design quality through rigorous design reviews, coding standards, and RTL maintainability practices.
  • Collaborating closely with verification, validation teams to ensure smooth IP integration and silicon success.
  • Coaching and developing engineers through handson technical mentoring, design feedback, and career development discussions.
  • Promoting a culture of technical ownership, accountability, and continuous improvement within the team.
  • Identifying opportunities to improve AI- driven design methodologies, workflows, and productivity, while keeping focus on design execution.
  • Communicating design status, technical risks, and tradeoffs effectively to senior management and crossfunctional stakeholders.

The Impact You Will Have:

  • Deliverindustryleading USB digital IPwith high performance, robustness, and scalability.
  • Drive strong architectural and design execution for USB IP used by leading customers.
  • Improve design quality, predictability, and execution efficiency through strong technical leadership.
  • Build and lead a highly capable ASIC digital design team with deep USB expertise.
  • Strengthen Synopsys' position as a leader in highspeed interface IP across commercial, enterprise, and automotive markets.

Requirements

  • Bachelor's degree in Electrical Engineering (BSEE) with 12+ years of experience, or Master's degree (MSEE) with 10+ years.

  • Demonstrated experience as ateam lead or people managerin an ASIC digital design environment.

  • Extensive handson ASIC RTL design experience, with direct ownership of complex digital designs.

  • Deep expertise in USB digital design and architecture or similar protocols.

  • Strong understanding of ASIC design fundamentals including clocking, resets, lowpower techniques, and design for test.

  • Experience with AI-driven tools, flows and methodologies. Familiarity with scripting languages (Perl, TCL, Python) for design automation is a plus.

About the company

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S. Synopsys maintains a workplace where all personnel, customers, and vendors are treated with dignity, fairness, and respect. We maintain worldwide policies in our Work Rules Policy, which is applicable to all employees in furtherance of these principles. We pride ourselves on providing a healthy and productive work environment that is free from discrimination and harassment based on race, color, religion, gender, gender identity, sexual orientation, marital status, veteran status, age, national origin, citizenship, ancestry, physical or mental disability, pregnancy, medical condition, and any other characteristic protected by law. For applicants and employees with disabilities, we also make reasonable accommodations consistent with applicable laws and regulations. We are each expected to do our part to create a healthy and productive work environment for everyone. This includes bringing issues to management's attention when you believe certain conditions are distracting from a good work environment. Our Work Rules Policy also allows you to raise concerns with other Synopsys managers. If employees are still unable to resolve their concerns, their disputes may be resolved through our Internal Issue Resolution Process Policy. In addition, all managers and employees in positions of authority have a special obligation to maintain and support a healthy and productive work environment.

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