Staff PMIC Design Engineer

We are seeking a Staff Engineer, Analogue PMIC Design to serve as a senior individual contributor within an ASIC engineering organization. This role is responsible for end-to-end ownership of analog power management blocks, including architecture definition, circuit design, simulation, verification, and documentation. The Staff Engineer partners closely with system architects, digital design, and verification teams to deliver fully validated PMIC IP used in large scale consumer SoCs. This position focuses on designing power blocks such as SMPS and LDOs, solving complex analog problems under tight power and area constraints, and ensuring designs meet performance across all process and voltage corners., * Definition of the architecture for the complex Power-management blocks, plan and execute the development of the blocks and providing the necessary documentation to different departments for the characterization of the block.

• Responsible for the delivering the fully verified blocks and may get involved in the verification of power-management subsystems within the Analogue section of a chip
• Solves complex problems in a tightly constrained environment;
• Fully competent in Analogue design for complex sub-cells and small subsystems;
• Keeps abreast of new developments and is technical expert in the design of analogue sub-cells;
• Ensures quality of the solution; works with macro lead to ensure timely delivery of subsystems

• Bachelor's degree, master's degree, or PHD in Science, Engineering, or related field
• 10+ years of experience in analog or mixed signal IC design
• Experience of using Cadence and Mentor analogue design and verification tools
• hands on ownership of PMIC or power related IP blocks
• Experience delivering fully verified blocks to tape out
• Experience on low power consumer or mobile SoCs - Experience supporting bring up or validation teams
• Design experience of Key Power management IPs like SMPS, LDOs
• Experience with additional power blocks such as bandgaps, references, charge pumps, or clock generators
• Exposure to automotive or high reliability power designs
• Familiarity with low power system level architecture tradeoffs
• Familiarity with CMOS process technologies