3D Heterogeneous Integration Design Enablement...
Role details
Job location
Tech stack
Job description
GlobalFoundries Fab8 is seeking a motivated R&D design enablement engineer to become part of our state-of-the-art 300mm fabrication facility in Malta, New York . This role will entail 3D heterogeneous integration (3DHI) design enablement to enable our next-generation advanced packaging R&D efforts, which include wafer - to - wafer bonding, die - to - wafer bonding , TSV/TOV and interposer development.
Essential Responsibilities:
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P ublish D esign M anual (DM) specifications based on failure modes identified for packaging required by the product lines in partnership with the unit process and R&D engineers.
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DM is a collection of all technology restrictions (geometry rules, electrical rules, etc.) that must be followed for an integrated circuit (IC) design to be manufacturable.
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Advanced packaging liaison to the DM and PDK ( Process D esign K it) teams to translate packaging requirements to a device enabl e ment specification covering: design rules , library device ( TSV) layouts, layout vs schematic( LVS) requirements , device model terminals.
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Develop expertise in drafting test vehicle content specifications and the associated tapeout process (including mask reviews ).
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Develop expertise in drafting test specifications for test vehicle content (macros); engage with the test teams (inline and lab) to ensure alignment on test requests.
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Collaborate with vendors and OSATs (Outsourced Assembly and Test) on design (test vehicles, masks).
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Facilitate a dvanced p ackaging design interactions between the product lines/ fab teams and customers.
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Work and collaborate with other teams regarding different assignments as needed.
Other Responsibilities:
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Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
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Other duties as assigned by manager.
Requirements
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Education - PhD with completed defended thesis in Electrical Engineering and Materials Science or related field from an accredited degree program.
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Must have at least an overall 3.0 GPA and proven good academic standing.
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Language Fluency - English (Written & Verbal).
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Travel - Up to 1 0%.
Preferred Qualifications:
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Prior-relat ed internship or co-op experience in design or EDA/design enablement
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Fundamental knowledge of semiconductor packaging process modules and integration.
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Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
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Project management skills, i.e. the ability to innovate and execute on solutions that matter; the ability to navigate ambiguity.
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Strong written and verbal communication skills .
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Strong planning & organizational skills.