Engineer Digital 3

Artech Information Systems LLC
San Diego, United States of America
3 days ago

Role details

Contract type
Temporary contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Compensation
$ 187K

Job location

San Diego, United States of America

Tech stack

Bash
Boolean Algebra
Software Debugging
Linux
Perl
Field-Programmable Gate Array (FPGA)
Make (Software)
Regression Testing
Release Management
Software Requirements Analysis
System Testing
Tcl (Programming Language)
VHDL
Scripting (Bash/Python/Go/Ruby)
Software Defined Radio

Job description

  • 12 or more years of professional technical experience.
  • Hands-on technical leadership and mentoring a team of 2-4 VHDL verification engineers.
  • Define and maintain digital logic design verification frameworks and architectures for software-defined radio systems.
  • Develop a verification plan based on digital logic design requirements and design specifications.
  • Simulate and verify FPGA logic designs, requirements, and perform system validation.
  • Analyze and debug simulation failures, determine root causes of bugs, and work with designers to resolve issues.
  • Perform regression testing and generate verification metrics and reporting.
  • Operate in a team environment with 5-7 engineers.

Requirements

  • Experience in VHDL design and verification methodologies for DoD communications systems.
  • FPGA deployable product process experience (requirements definition, conceptual design, detailed design, verification, and production release).
  • Experience with technical management of tasks, forecasting, and estimating schedules to ensure completion to meet schedule and quality standards.
  • Demonstrated strong analytical skills and the ability to prioritize assignments according to program goals.
  • Demonstrated ability to coordinate and communicate effectively with members of cross-functional teams and program management.
  • Experience developing verification plans, functional tests, test benches, and bus functional models.
  • Experience using Siemens Questa Simulator., * Active Security Clearance.
  • Experience with leading a team with various levels of experience and skills.
  • Experience with the management of cost and metric reporting.
  • Experience with functional verification methodology using OSVVM for the full life cycle of products.
  • Experience with scripting languages for Verification automation in a Linux environment (Perl, TCL, Bash, and Makefile).
  • Experience using Siemens formal applications such as Lint, Inspect, and CDC.
  • Ability to hold special access program clearances.

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