ASIC DFT CDC Constraints Engineer
CYNET SYSTEMS INC.
Milpitas, United States of America
3 days ago
Role details
Contract type
Permanent contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
Senior Compensation
$ 208KJob location
Remote
Milpitas, United States of America
Tech stack
Code Coverage
Computer Engineering
Software Debugging
Static Timing Analysis
System on a Chip
Application Specific Integrated Circuits
Job description
- Own and develop SDC/SSTA constraint strategies for functional and DFT scan-mode operations.
- Work on CDC violations impacting scan-shift failures and at-speed test escapes.
- Perform timing analysis and sign-off activities using industry-standard STA tools.
- Develop and maintain DFT-mode timing constraints for scan shift and capture operations.
- Analyze and resolve metastability and synchronization issues across clock domains.
- Debug and resolve scan-mode X-propagation issues.
- Collaborate with DFT, STA, and design teams for timing closure and test coverage improvements.
Requirements
- 10+ years of ASIC/SoC experience with 5+ years in SDC constraint development and STA sign-off.
- Strong expertise in CDC synchronization structures and SDC constraint representation.
- Hands-on experience with PrimeTime, Tempus, or Fusion Compiler.
- Experience with SpyGlass CDC or JasperGold CDC for structural CDC analysis.
- Strong understanding of metastability, MTBF, and synchronizer settling time budgets.
- Experience constraining Gray-code FIFO pointers and pulse synchronizers.
- Solid understanding of scan insertion, scan chain stitching, and ATPG flow.
- Experience authoring DFT-mode SDC views including shift, capture, and at-speed modes.
- Familiarity with Tessent or Synopsys DFTC ATPG toolchain.
- Ability to debug X-propagation issues in scan mode arising from unconstrained CDC paths., * 10+ years of experience in ASIC/SoC development.
- 5+ years of hands-on experience in SDC constraint engineering and STA sign-off.
- Extensive experience in CDC theory, ATPG methodology, and timing closure., * Strong analytical and debugging skills.
- Ability to work in highly complex multi-clock SoC environments.
- Excellent understanding of CDC methodologies and DFT architectures.
Skills:
- PrimeTime
- Tempus
- Fusion Compiler
- SpyGlass CDC
- JasperGold CDC
- Tessent
- Synopsys DFTC
- ATPG
- STA
- CDC Analysis
- SDC Constraints
- ASIC/SoC Design
Qualification and Education:
- Bachelor s or Master s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related technical field.