Logic Designer Integrator Tester
Role details
Job location
Tech stack
Job description
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Define reference design / example architectures to best demonstrate features of Rambus PCIe / CXL controller IP
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Participate in FPGA prototyping and hardware validation
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Run and improve quality checks (ASIC synthesis, CDC/RDC/Linting, simulation)
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Collaborate with a worldwide team
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Contribute to technical improvements on all aspects of the IP design domain
Requirements
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RTL coding : Verilog / VHDL
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Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
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Good English skills, communication skills, and willingness to work with an international team. skills, and willingness to work with an international team.
Additional Desirable skills
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Knowledge of ASIC and FPGA design flow and tools (ASIC Synthesis, CDC / RDC / Linting, Quartus, Vivado
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CI : Python / Jenkins / GIT
Benefits & conditions
Rambus offers a competitive compensation package, including base salary, bonus,
equity
and employee benefits.
At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have
equitable
access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our
best work
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.
Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans
during