Sr. FPGA Engineer

Accord Technologies Inc
Melbourne, United States of America
3 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior
Compensation
$ 165K

Job location

Melbourne, United States of America

Tech stack

Automation of Tests
Unix
C++
Code Coverage
Linux
Perl
Ethernet
Field-Programmable Gate Array (FPGA)
Python
PCI Express
Rapid Prototyping Process
SystemVerilog
Systems Integration
Verilog
VHDL
CPLD
Vivado
Scripting (Bash/Python/Go/Ruby)
Data Server Interface
Application Specific Integrated Circuits
Hardware Testing

Job description

The Electrical Engineer designs, tests and documents safety-critical hardware. Responsible for developing and supporting FPGA/CPLD designs through all phases of design and system integration for high-reliability embedded aerospace and ground based vehicle systems applications. Skills Must Have: Requirements capture, decomposition, and traceability. Develop RTL design code and simulation in VHDL, Verilog, and/or System Verilog. Develop Hardware test case, procedures and integration Define the verification strategy to be applied, such as on-Hardware verification environment, test frameworks and test tools Perform ASIC/FPGA/SoPC verification using inspection, analysis, simulation, and test methods. Creation of DO-254 DAL-A certification artifacts for Airborne Electronic Hardware (AEH). Ability to work with minimal supervision, as part of a team of engineers with a variety of skills and backgrounds, located throughout the world and matrixed into projects with aggressive schedules and frequent milestones. Experience with DO-254 processes and design assurance activities for ASIC, FPGA, and/or SoPC developments. Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, code coverage, UVM, SystemVerilog). Conduct and/or participate in peer reviews throughout product lifecycle. Participate in FAA SOI audits. Communicate well with a wide variety of individuals including Engineering, Program Management, internal leadership and customers. Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow. Provide guidance or mentor other engineers with a variety of skills and backgrounds.

Requirements

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience. Experience writing RTL and test benches using VHDL, UVM, Verilog, or SystemVerilog. Experience with Linux (or Unix), scripting, C/C++, Python, and/or Perl. Experience using FPGA specific tools (e.g. Questasim, Vivado, Libero, Synplify Pro, etc.) Experience with data interfaces (PCIe, DDR, I2C, Ethernet, CDN, ARINC-429, etc.) Must have skills: No. of year of experience FPGA D0-254 System Verilog designs VHDL UVM test benches

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