SoC Performance Architect
Role details
Job location
Tech stack
Job description
Lead MPU and SoC performance pathfinding, modeling, simulations, and projections for current and future platforms. Develop system-level models to evaluate and optimize performance (throughput, latency, QoS, power) across multiple design options. Collaborate cross-functionally with hardware, firmware, and validation organizations to ensure end-to-end product quality, performance, and reliability. Generate workloads for target applications and optimize these workloads within hardware constraints Drive performance metrics and analysis for central compute ECU workloads Conduct theoretical analysis and return on investment of new features or proof of concept Manages Neural Network benchmark criteria and competitive analysis Work with SoC Architect and software teams to optimize hardware for system workloads within performance, power, reliability, and cost constraints. Support SoC microarchitecture definition and specifications Support hardware engineering in design, system architecture, and ECU development phases.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering or related field A minimum of 8 years relevant experience Strong understanding of computer architecture fundamentals Proficient with system performance modeling and simulation analysis Successful first-pass SoC or MPU development record Preferred Qualifications Master's degree, Automotive or Industrial experience Direct work with ARM 32/64-bit, power management, high-speed interfaces, memory, video/audio Experience with memory controller designs for LPDDR5, DDR5, LPDDR6 Strong background in building fast, accurate SoC performance models Strong understanding of embedded electronics design constraints Soft Skills Strong analytical and conceptual thinking with a track record of innovation Excellent communication skills and the ability to collaborate effectively across global, multi-disciplinary teams. Passion for architecting SoC or MPU solutions that redefine performance and efficiency in embedded computing